The basic single-cycle MIPS implementation in the figure above can only implement some instructions. New instructions can be added to an existing Instruction Set Architecture (ISA), but the decision whether or not to do that depends, among other things, on the cost and complexity the proposed addition introduces into the processor datapath and control

Instruction: LWI Rt, Rd(Rs) Interpretation: Reg[Rt] = Mem[Reg[Rd] + Reg[Rs]] [4 pts] a. Which existing blocks (if any) can be used for this instruction? [3 pts] b. [True/False]: New functional blocks (if any) are needed for this instruction. [1 pt]

Branch 4 Add Add ALU operation Data Register # Register # Register # RegWrite||| MemWrite PCAddress Instruction Registers ALU Address Zero Instruction memor)y Data memory DataM MemRead Control