Question: The testbench.sv is below `default_nettype none module tb_mux; reg [1:0] mux2_in; reg mux2_sel; wire mux2_out; reg [3:0] mux4_in; reg [1:0] mux4_sel; wire mux4_out; mux2 mux2_dut(

The testbench.sv is below `default_nettype none module tb_mux; reg [1:0] mux2_in;

The testbench.sv is below

`default_nettype none

module tb_mux;

reg [1:0] mux2_in; reg mux2_sel; wire mux2_out;

reg [3:0] mux4_in; reg [1:0] mux4_sel; wire mux4_out;

mux2 mux2_dut( mux2_in, mux2_sel, mux2_out ); mux4 mux4_dut( mux4_in, mux4_sel, mux4_out );

initial begin $dumpfile("dump.vcd"); $dumpvars(0, mux2_dut); $dumpvars(0, mux4_dut); $display("TESTING mux2"); #1 mux2_in = 2'b10; mux2_sel = 0; #1 assertEquals(mux2_out, 0);

#1 mux2_sel = 1; #1 assertEquals(mux2_out, 1);

$display("TESTING mux4"); #1 mux4_in = 4'b1010; mux4_sel = 0; #1 assertEquals(mux4_out, 0);

#1 mux4_sel = 1; #1 assertEquals(mux4_out, 1);

#1 mux4_sel = 2; #1 assertEquals(mux4_out, 0);

#1 mux4_sel = 3; #1 assertEquals(mux4_out, 1);

#1 $finish(); end

task assertEquals; input val, expected; begin if (val == expected) $display("[TEST][PASSED]"); else $display("[TEST][FAILED] Got %03b, expected %03b", val, expected); end endtask

endmodule

The design.sv

`default_nettype none

module mux2(input [1:0] in, input sel, output out);

endmodule

module mux4(input [3:0] in, input [1:0] sel, output out);

endmodule

Part 2: Multiplexers Multiplexers (also called muxes) are an important part of computer design, and have a wide variety of applications. The purpose of a multiplexer is to select 1 of n inputs to output. So naturally, it has some set number of inputs to choose from, and then it as log(n) bits to use as a selection mechanism. Here is the block diagram for a 2-way mux: in[1]-muxout sel For this lab assignment you will construct a mux for 2-1 and 4-1 muxes https://www.edaplayground.com/x/4C28

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