Write the complete modular Verilog code for a module that has a clock input, two N-bit inputs, A and B and a (2N+1)-bit output C. The module should concatenate the two inputs so that A contains the MSB and B contains the LSB, and then it should add this new value to itself to create the output C. The output C should be registered so that the output only changes on the falling edge of the clock. You must use a single parameter with a default size of 8 for the size of A and B and a single localparam for the size of C. Write a testbench to correctly test the module you wrote in the previous question with at least 2 different sets of test input values for A and B by displaying A, B, and C to the terminal. Make your testbench so that A and B are both 12-bit numbers. Note, you do not need to have completed the previous question to attempt this question, you have all you need to know about how to instantiate and test the module by the previous question's instructions alone. Write the complete modular Verilog code for a module that has a clock input, two N-bit inputs, A and B and a (2N+1)-bit output C. The module should concatenate the two inputs so that A contains the MSB and B contains the LSB, and then it should add this new value to itself to create the output C. The output C should be registered so that the output only changes on the falling edge of the clock. You must use a single parameter with a default size of 8 for the size of A and B and a single localparam for the size of C. Write a testbench to correctly test the module you wrote in the previous question with at least 2 different sets of test input values for A and B by displaying A, B, and C to the terminal. Make your testbench so that A and B are both 12-bit numbers. Note, you do not need to have completed the previous question to attempt this question, you have all you need to know about how to instantiate and test the module by the previous question's instructions alone