Write a test bench for the floating-point adder of Figure 7-14.

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Digital Systems Design Using Verilog

ISBN: 978-1285051079

1st edition

Authors: Charles Roth, Lizy K. John, Byeong Kil Lee

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Question Posted: Jan 22, 2019 12:42 PM

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Write a test bench for the floating-point adder of Figure 7-14.

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module fpaddertestbench TestNum output reg TestNum reg CLK ST reg 31 0 INPUT wire DONE OVF UNF wire 31 0 SUM parameter N 15 reg 31 0 addendarr 1 N reg ...View the full answer

Digital Systems Design Using Verilog

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