Question: Assume that logic blocks needed to implement a single cycle processor's datapath have the following latencies - XEM add MUX ALU Regs D-Mem Sign-Extend Shift-left-2

Assume that logic blocks needed to implement a single cycle processor's

Assume that logic blocks needed to implement a single cycle processor's datapath have the following latencies - XEM add MUX ALU Regs D-Mem Sign-Extend Shift-left-2 350 355 20 90 90 200 15 10 If the only thing we need to do in a processor is fetch consecutive instructions (Figure 4.6). what would the cycle time be? Do NOT insert units

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