Question: (b) Based on the Verilog coding in Figure Q4(b), draw the equivalent logic circuit. module question4 (out, i0,il,s); output out; input i0, il; input

(b) Based on the Verilog coding in Figure Q4(b), draw the equivalent

(b) Based on the Verilog coding in Figure Q4(b), draw the equivalent logic circuit. module question4 (out, i0,il,s); output out; input i0, il; input s; wire sbar, yl, y2; not n1 (sbar,s); and al(yl,i0,sbar): and a2(y2,i1,s); or ol (out.yl.y2); endmodule Figure Q4(b) [3 marks]

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