for this code Could you draw a combinational logic diagram?

library IEEE; use IEEE.STD$\_$LOGIC$\_1164.$ALL; use IEEE.STD$\_$LOGIC$\_$ARITH.ALL; use IEEE.STD$\_$LOGIC$\_$UNSIGNED.ALL; entity sequential$\_$division is Port $($ clk : in STD$\_$LOGIC; rst : in STD$\_$LOGIC; A : in STD$\_$LOGIC$\_$VECTOR $(2$ downto $0)$; B : in STD$\_$LOGIC$\_$VECTOR $(2$ downto $0)$; Q : out STD$\_$LOGIC$\_$VECTOR $(2$ downto $0)$; R : out STD$\_$LOGIC$\_$VECTOR $(2$ downto $0))$; end sequential$\_$division; architecture Behavioral of sequential$\_$division is signal remainder : STD$\_$LOGIC$\_$VECTOR $(3$ downto $0)$ :$="0000"$; signal quotient : STD$\_$LOGIC$\_$VECTOR $(2$ downto $0)$ :$="000"$; signal temp$\_$B : STD$\_$LOGIC$\_$VECTOR $(3$ downto $0)$; signal subtract$\_$result : STD$\_$LOGIC$\_$VECTOR $(3$ downto $0)$; signal cmp$\_$flag : STD$\_$LOGIC; begin process$($clk$,$ rst$)$ begin if rst $=\text{'}1\text{'}$ then remainder $<="0000"$; quotient $<="000"$; elsif rising$\_$edge$($clk$)$ then if $($unsigned$($remainder$)>=$ unsigned$($temp$\_$B$))$ then subtract$\_$result $<=$ std$\_$logic$\_$vector$($unsigned$($remainder$)-$ unsigned$($temp$\_$B$))$; quotient $<=$ std$\_$logic$\_$vector$($unsigned$($quotient$)+1)$; remainder $<=$ subtract$\_$result; end if; end if; end process; $--$ Assign inputs to temporary registers temp$\_$B $<="000"$ & B; $--$ Extend B to $4$ bits remainder $<="000"$ & A; $--$ Extend A to $4$ bits $--$ Output assignments Q $<=$ quotient; R $<=$ remainder$(2$ downto $0)$; $--$ Take lower $3$ bits as remainder end Behavioral;