Givell the following MIPS assembly like code:

Li R$8,8$

LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

Sub R$7,$ R$1,$ R$3$

LW $R4,10($R$7)$

SW R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,$ L

Also, given the following latencies for each stage:

IF: $80n,$ ID: $30n$ s$,$ EX: $50n,$ MEM: $85n$ s$,$ and WB: $35n$ s

What is the total number of stall cycles needed when running this code on a MIPS Pipelined

CPU without data forwarding and the branch resolved in the EX Stage and initialized to be

Not Taken. Ignore initial pipeline fill cycles.AQ O O$,$ given the following latencies for each stage:

IF: $80n$ s$,$ ID: $30n$ s$,$ EX: $50n$ s$,$ MEM: $85ns,$ and WB: $35n$ s

What is the total number of stall cycles needed when running this code on a MIPS Pipelined

CPU without data forwarding and the branch resolved in the EX Stage and initialized to be

NoI Taken. Ignore initial pipeline fill cycles.

A$.22$

B$.20$

C$.12$

D$.24$

E$.10$