Given the following MIPS assembly like code:

Li R$8,8$

L: $,$ LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

SUb R$7,$ R$1,$ R$3$

LW R$4,10($R$7)$

Sw R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,1.$

Assume the code run on a Pipelined MIPS CPU with the using of full data

forwarding and the branch resolved in the ID Stage and initialized to be

Not Taken. The compiler can reorder the code with:

A$.$ Two stall cycles

B$.$ Zero stall cycles

C$.$ Cannot be reordered

D$.$ One stall cycle

E$.$ None of the answers