Given the following MIPS assembly like code:

Li R$8,8$

L: $,$ LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

Sub R$7,$ R$1,$ R$3$

LW R$4,10($R$7)$

SW R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,$ L

Assume the code run on a Pipelined MIPS CPU with the using of full data forwarding and the branch resolved in the ID Stage and initialized to be Not Taken. The compiler can reorder the code with: