Given the following MIPS assembly like code: Li R$8,8$ L: Lw R$2,$ R$3,$ R$7$ Add R$1,$ R$2,$ R$3$ Sub R$7,$ RI$,$ R$3$ Lw R$4,10($R$7)$ SAN R$4,20($R$1)$ Subi R$8,$ R$8,4$ BNEQZ R$8,$ L

Also, given the following latencies for each stage: IF: $8$Ons, ID: $3$Ons, EX: $5$Ons, MEM: $85$ns$,$ and WB: $35$ns What is the total number of cycles needed when running this code on a MIPS Pipelined CPU with the using of full data forwarding and the branch resolved in the ID Stage and initialized to be Taken. Ignore initial pipeline fill cycles.

A$\mathrm{.}18$ B$\mathrm{.}17$ C$\mathrm{.}32$ D$\mathrm{.}16$ E$.30$