Given the following MIPS assembly like code:

Li R$8,8$

L: $,$ LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

SUb R$7,$ R$1,$ R$3$

LW R$4,10($R$7)$

SW R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,$ L

Also, given the following latencies for each stage:

IF: $80ns,$ ID: $30ns,$ EX: $50ns,$ MEM: $85ns,$ and WB: $35ns$ fill cycles.

A$.18$

B$.17$

C$.32$

D$.30$

E$.16$