Question: Given the following MIPS assembly like code: Li R 8 , 8 L: , LW R 2 , R 3 , R 7 Add R
Given the following MIPS assembly like code:
Li R
L: LW R R R
Add R R R
Sub R R R
LW RR
SWRR
Subi R R
BNEQZ R L
Also, given the following latencies for each stage:
IF: ns ID: ns EX: ns MEM: and WB: ns
What is the average CPI when running this code on Multicycle MIPS CPU with the above latencies?
A
B None of the answers
C
D
E
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