Mulicyle mips cou

Given the following MIPS assembly like code:

Li R$8,8$

LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

Sub R$7,$ R$1,$ R$3$

LW R$4,10($R$7)$

SW R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,$ L

Also, given the following latencies for each stage:

IF: $80ns,$ ID: $30n,$ EX: $50ns,$ MEM: $85n,$ and WB: $35n$ s

What is the total number of cycles needed when running this code on ideal MIPS Pipelined CPU?

A$.19$

B$.15$

c$.$ None of the answers

D$.20$

E$.16$