Given the following MIPS assembly like code:

Li R$8,8$

Time left $0$:$42$:$3$

L: $,$ LW $R2,R3,R7$

Add R$1,$ R$2,$ R$3$

Sub R$7,$ RI$,$ R$3$

$($w R$4,10($R$7)$

Sw R$4,20($R$)]$

Subi R$8,$ R$8,4$

BNEQZ R$8,$ L

Also, given the following latencies for each stage:

IF: $80$ ns$,$ ID: $30$ ns$,$ EX: $50$ ns$,$ MEM: $85n,$ and WB: $35$ ns

What is the total number of stall cycles needed when running this code on a MIPS Pipelined CPU without data forwarding and the branch resolved in the EX Stage and initialized to be NoI Taken, Ignore initial pipeline fill cycles.

A$.20$

B$.24$

C$.10$

D$.12$

E$.22$