How do you create a 16bit Ripple Carry Adder baised on the verilog code below?

module RCA16bit(A, B, Cin, S, Cout);

endmodule

module RCA4bit(A, B, Cin, S, Cout);

input Cin;

input [3:0] A, B;

output [3:0] S;

output Cout;

wire x1, x2, x3;

fulladder stage0 (.a(A[0]), .b(B[0]), .Cin(Cin), .s(S[0]), .Cout(x1));

fulladder stage1 (.a(A[1]), .b(B[1]), .Cin(x1), .s(S[1]), .Cout(x2));

fulladder stage2 (.a(A[2]), .b(B[2]), .Cin(x2), .s(S[2]), .Cout(x3));

fulladder stage3 (.a(A[3]), .b(B[3]), .Cin(x3), .s(S[3]), .Cout(Cout));

endmodule

module fulladder(a, b, Cin, s, Cout);

input a, b, Cin;

output s, Cout;

assign s = a ^ b ^ Cin;

assign Cout = (a&b) | (a&Cin) | (b&Cin);

endmodule

module mux2to1(a, b, sel, f);

input a, b, sel;

output reg f;

always @ (a, b, sel)

if (sel == 0) f = a; else f = b;

endmodule