$1.$ Create a $6-$Bit Ripple Carry Adder Module called "Adder$6"$:

a$.$ What inputs, outputs, and wires would you define this module with, and what would be the sizes of the vectors? $($Hint: look at Exercise $2$ in making the $4-$bit adder$)$

b$.$ How many EullAdder instances do we need? What would you name them?

Paste below your Adder$6$ module code:

$2.$ Create a $6-$Bit Ripple Carry Adder testbench Module called "Adder$6\_$tb$"$:

a$.$ What inputs, outputs, and wires would you define this testbench module with, and what would be the sizes of the vectors? $($Hint: Again, check Exercise $2.)$

b$.$ What would be the dut statement to instantiate the Adder$6$ module to this testbench module?

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c$.$ Test Cases:

i$.$ What are the binary values of $3$ and $8?$

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ii$.$ What would be the simulation statement for adding these two numbers in binary? $(\backslash (\backslash$mathrm$\{$sin$\}=0\backslash ))$

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iii. What is the command to end the simulation at the end of all test cases?

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iv$.$ Record the expected and simulated outputs in the table below

$\backslash$begin$\{$tabular$\}\{|$l$|$l$|$l$|$l$|$l$|$l$|$l$|$l$|$l$|\}$

$\backslash$hline A $($Decimal$)$ & B $($Decimal$)$ & A $($Binary$)$ & B $($Binary$)$ & cin & $\backslash$begin$\{$tabular$\}\{$l$\}$

Expected $\backslash \backslash$

Sum

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$l$\}$

Simulated $\backslash \backslash$

Sum

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$l$\}$

Expected $\backslash \backslash$

cout

$\backslash$end$\{$tabular$\}$ & $\backslash$begin$\{$tabular$\}\{$l$\}$

Simulated $\backslash \backslash$

cout

$\backslash$end$\{$tabular$\}\backslash \backslash$

$\backslash$hline $1$ & $1$ & & & $0$ & & & & $\backslash \backslash$

$\backslash$hline $3$ & $5$ & & & $0$ & & & & $\backslash \backslash$

$\backslash$hline $32$ & $1$ & & & $1$ & & & & $\backslash \backslash$

$\backslash$hline $37$ & $51$ & & & $0$ & & & & $\backslash \backslash$

$\backslash$hline $15$ & $15$ & & & $0$ & & & & $\backslash \backslash$

$\backslash$hline $62$ & $1$ & & & $1$ & & & & $\backslash \backslash$

$\backslash$hline $21$ & $22$ & & & $1$ & & & & $\backslash \backslash$

$\backslash$hline

$\backslash$end$\{$tabular$\}$ v$.$ Paste below your testbench module code below using the test cases from the table above:

vi$.$ Paste a screenshot of your simulation waveforms for all input combinations: