Question: In the following Verilog code: always @ ( posedge clk ) begin if ( reset ) begin count 0 ; end else begin count count

In the following Verilog code:
always @(posedge clk) begin if (reset) begin
count 0;
end else begin
count count +1 ;
if (count ==4'h F) begin count 0;
end
end
end
What will be the value of count after 12 clock cycles if reset is 0?
In the following Verilog code: always @(posedge clk) begin if (reset)

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