Question: module test ( in , slt , out ) ; input in , [ 1 : 0 ] slt; output reg [ 3 : 0

module test(in,slt,out); input in,[1:0]slt; output reg [3:0] out; always @ (in or slt) begin case (slt)2'b00: out[0]=in; 2'b01: out[1]=in; 2'b10: out[2]=in; 2'b11: out[3]=in; endcase end endmodule A. Give the value of the output (value of each bit) for the following input values: in=0, slt[1:0]=10 in=0, slt[1:0]=01 in=1, slt[1:0]=10 B. If we modify the always block as follows: always @ (in and slt) begin case (slt)2'b00: out[0]=in; 2'b01: out[1]=in; 2'b10: out[2]=in; 2'b11: out[3]=in; endcase end What will be the values of the output for the following input values? in=0, slt[1:0]=10 in=0, slt[1:0]=01 in=1, slt[1:0]=10 C. The code given in part a) corresponds to a de-multiplexer where one output is selected by the selector to get the value of the input. If we add one more bit for the slt input, in a way that the chosen output corresponds to the modulus of the slt input value, ex.: if the slt input value is 101(i.e.5 in decimal), the selected output will be out[3] because 3%8=3. Mo

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