Questions and Answers of Logic And Computer Design Fundamentals

A 36-bit floating- point number consists of 26 bits plus sign for the fraction and 8 bits plus sign for the exponent. What are the largest and smallest positive nonzero quantities for normalized
There are many possible formats for floating point numbers. Consider the following 10-formatwhere the sign ield is one bit (1: negative, 0: positive), the exponent ield is 4 bits with an excess 8
A 4-bit exponent uses an excess 7 number for the bias. List all biased binary exponents from +8 through -7.
The IEEE standard double-precision floating-point operand format consists of 64 bits. The sign occupies 1 bit, the exponent has 11 bits, and the fraction occupies 52 bits. The exponent bias is 1023
It is necessary to branch to ADRS if the bit in the least significant position of the operand in a 16-bit register is equal to 1. Show how this can be done with the TEST (Table 9-7) and BNZ (Table
The IEEE standard single- precision floating- point format shown in Figure 9-8 uses 32 bits. Figure 9-8(a) What is the 8-digit hexadecimal representation of the decimal number -9.359375?(b) What
Prove that if the equality 2x = 10y holds, then y = 0.3x. Using this relationship, calculate the largest and smallest normalized floating- point numbers in decimal that can be accommodated in the
Consider the two 8-bit numbers A = 10110110 and B = 00110111.(a) Give the decimal equivalent of each number, assuming that (1) they are unsigned and (2) they are signed 2s complement.(b) Add the
The program in a computer compares two signed 2s complement numbers A and B by performing subtraction A - B and updating the status bits. For operands let A = 11011010 and B = 01110110,(a) Evaluate
Repeat Problem 9-28 with A = 10100100 and B = 10101001.Problem 9-28The program in a computer compares two signed 2s complement numbers A and B by performing subtraction A - B and updating the status
The program in a computer compares two unsigned numbers A and B by performing a subtraction A - B and updating the status bits. For operands let A = 01011101 and B = 01011100,(a) Evaluate the
The top of a memory stack contains 5000. The stack pointer SP contains 4000. A two- word procedure call instruction is located in memory at address 2000, followed by the address ield of 502 at
What are the basic differences between a branch, a procedure call, and a program interrupt?
A computer responds to an interrupt request signal by pushing onto the stack contents of the PC and the current PSR. The computer then reads new PSR contents from memory from the location given by
A pipelined datapath is similar to that in Figure 10-1(b), but with the delays from the top to the bottom replaced by the following values: 0.5 ns, 0.5 ns, 0.1 ns, 0.1 ns, 0.7 ns, 0.1 ns, and 0.1 ns.
Assume that a computer has eight general purpose registers R0–R7, a stack pointer register SP, and program counter PC. If the calling convention for this computer is that registers R0 and R1 are
For each of the RISC operations in Table 10-1, list the addressing mode or modes used.Table 10-1 Operation No Operation Move A Add Subtract AND OR Exclusive-OR Complement Add Immediate Subtract
A program consisting of a sequence of ten instructions without branch or jump instructions is to be executed in an 8-stage pipelined RISC computer with a clock period of 0.5 ns. Determine(a) The
Repeat Problem 10-6 for the instruction LSR R6 R2 001D with R6 containing 00000000 and R2 containing 01ABCDEF.Problem 10-6For the RISC CPU in Figure 10-8, manually simulate, in hexadecimal, the
The sequence of seven LDI instructions in the register-number program with the pipeline execution pattern given on page 540 is fetched and executed. Manually simulate the execution by giving, for
Simulate the operation of the barrel shifter in Figure 10-9 for each of the following shifts and A = 3DF3CB4A16. List the hexadecimal values on the 47 lines, 35 lines, and 32 lines out of the three
For the RISC CPU in Figure 10-8, manually simulate, in hexadecimal, the processing of the instruction ADI R1 R16 2F01 located in PC = 10F.Assume that R16 contains 0000001F. Show the contents of each
Repeat Problem 10-6 for the instruction SLT R7 R3 R5 with R3 containing 0000F001 and R5 containing 0000000F.Problem 10-6For the RISC CPU in Figure 10-8, manually simulate, in hexadecimal, the
Repeat Problem 10-6 for the instruction SIU R2 R2 635A with R2 containing 0A5FBC2B.Problem 10-6For the RISC CPU in Figure 10-8, manually simulate, in hexadecimal, the processing of the instruction
Use a computer-based logic minimization program to design the instruction decoder for a RISC from Table 10-3. Create an HDL model of your design and verify its correctness in simulation.Table 10-3
For the RISC design, draw the execution diagram for the following RISC program, and indicate any data hazards that are present: 1 MOVA 2 SUB 3 AND R7, R6 R8, R8, R6 R8, R8, R7
Draw the execution diagrams for the program in Problem 10-11, assumingProblem 10-11For the RISC design, draw the execution diagram for the following RISC program, and indicate any data hazards that
For the RISC design, draw the execution diagram for the following RISC program (with the contents of R7 nonzero after the subtraction), and indicate any data or control hazards that are present: 1
Rewrite the RISC programs in Problems 10-11 and 10-12, using NOPs to avoid all data and control hazards, and draw the new execution diagrams.Problem 10-11For the RISC design, draw the execution
Simulate the processing of the program in Problem 10-12 using the RISC CPU with data-hazard stall in Figure 10-12. Give the contents of each pipeline platform and the register file (the latter only
Repeat Problem 10-15 using the RISC CPU with data forwarding in Figure 10-13.Problem 10-15Simulate the processing of the program in Problem 10-12 using the RISC CPU with data-hazard stall in Figure
Design the constant unit in the pipelined CISC CPU by using the information given in Table 10-4 and multiple-bit multiplexers, AND gates, OR gates, and inverters. Create an HDL model of your design
Write microcode for the execution part of each of the following CISC instructions. Give both a register transfer description and binary or hexadecimal representations similar to those shown in Table
Repeat Problem 10-21 for the following CISC instructions that are specified by register transfer statements.Problem 10-21Write microcode for the execution part of each of the following CISC
Repeat Problem 10-22 for the following CISC instructions.Problem 10-22 Repeat Problem 10-21 for the following CISC instructions that are specified by register transfer statements.Problem 10-21Write
Repeat Problem 10-22 for the following CISC instructions.Borrow B is defined as the complement of the carry out, C.Problem 10-22Repeat Problem 10-21 for the following CISC instructions that are
Repeat Problem 10-21 for the CISC instruction, Memory Scalar Add. This instruction uses the contents of R[SB] as the vector length. It adds the elements of the vector with its least significant
Repeat Problem 10-21 for the CISC instruction, Memory Vector Add. This instruction uses the contents of R[SB] as the vector length. It adds the vector with its least signiicant element in memory
PADDB (Add Packed Byte Integers) is the mnemonic for an SSE SIMD instruction in the IA-32 architecture. In the RISC computer in this chapter, the equivalent instruction would add two 32-bit operands
(a) In the Core 2 Duo, each core can perform a PMINSW (Minimum of Packed Signed Word Integers) instruction with two 128-bit operands, placing the result back in the irst operand. For 16-bit words,
Find the formatted capacity of the hard drives described in the following table: Drive Heads A B 1 4 16 Cylinders 1023 8191 16383 Sectors/ Track 63 63 63 Bytes/ Sector 512 512 512
Estimate the time required to transfer a block of 1 MB (220 B) from a hard drive to memory given the following drive parameters: seek time, 8.5 ms; rotational delay, 4.17 ms; controller time,
How many I/O interface units of the type shown in Figure 11-6 can be addressed by using a 16-bit address, assuming(a) Each of the chip select (CS) lines is attached to a different address
Find the number of pixels and subpixels for LCD screens with the following actual screen sizes:(a) 1280 х 1024.(b) 1600 х 1200.(c) 1680 х 1050.(d) 1920 х 1200.
Assume that the transfers with strobing shown in Figure 11-7 are between a CPU on the left and an I/O interface on the right. There is an address coming from the CPU for each of the transfers, both
A different type of I/O interface does not have the RS1 and RS0 inputs. Up to two registers can be addressed by using a separate I/O read signal and I/O write signal for each address available.
Assume that the transfers with handshaking shown in Figure 11-8 are between a CPU on the left and an I/O interface on the right. There is an address coming from the CPU for each of the transfers,
Sketch the waveforms for the SYNC pattern used for USB and the corresponding NRZI waveform. Explain why the pattern selected is a good choice for achieving synchronization.
The following stream of data is to be transmitted by USB: 01111111001000000001101110000011(a) Assuming bit stuffing is not used, sketch the NRZI waveform.(b) Modify the stream by applying bit
The 8-bit ASCII word “Bye” is to be transmitted to a device address 39 and endpoint 2. List the Output and Data 0 packets and the Handshake packet for a Stall for this transmission prior to NRZI
What changes are needed in Figure 11-17 to make the four VAD values equal to the binary equivalent of 024, 025, 026, and 027?Figure 11-17 Interrupt register Highest 3 priority Lowest priority 1 1
Repeat Problem 11-13 for the word “Hlo” and a Handshake packet of type No Acknowledge.Problem 11-13The 8-bit ASCII word “Bye” is to be transmitted to a device address 39 and endpoint 2. List
Repeat Problem 11-18 for VAD values 122, 123, 124, and 125.Problem 11-18What changes are needed in Figure 11-17 to make the four VAD values equal to the binary equivalent of 024, 025, 026, and
Design parallel priority interrupt hardware for a system with six interrupt sources.
It is necessary to transfer 2048 words from a hard drive to a section of memory starting from address 4096. The transfer is by means of DMA, as shown in Figure 11-20.Figure 11-20(a) Give the initial
A priority structure is to be designed that provides vector addresses.(a) Obtain the condensed truth table of a 16 × 4 priority encoder.(b) The four outputs w, x, y, z from the priority encoder
Write a datalow Verilog description for the circuit in Figure 2-43 by using the Boolean equation for the output F and using Figure 2-34 as a model.Figure 2-43Figure 2-34
Find a logic diagram representing minimum 2-level logic needed to implement the Verilog datalow description in Figure 2-47. Note that complemented inputs are available.Figure 2-47
Using Figure 2-46 as a framework, write a structural Verilog description of the circuit in Figure 2-43. Replace X, Y, and Z with input [2:0] X. Compile and simulate your Verilog model for all eight
Using Figure 2-33 as a framework, write a structural Verilog description of the circuit in Figure 2-44. Compile and simulate your Verilog model for all 16 possible input combinations to verify your
Find a logic diagram that corresponds to the Verilog structural description in Figure 2-46. Note that complemented inputs are not available.Figure 2-46
Write a datalow VHDL description for the circuit in Figure 2-43 by using the Boolean equation for the output F. Figure 2-43
Find a logic diagram representing minimum two- level logic needed to implement the VHDL datalow description in Figure 2-45. Note that complemented inputs are available.Figure 2-45
Using Figure 2-28 as a framework, write a structural VHDL description of the circuit in Figure 2-44. Consult package func_prims in library lcdf_vhdl for information on the various gate components.
Using Figure 2-28 as a framework, write a structural VHDL description of the circuit in Figure 2-43. Replace X, Y, and Z with X (2:0). Consult package func_prims in library lcdf_vhdl for information
*Find a logic diagram that corresponds to the VHDL structural description in Figure 2-42. Note that complemented inputs are not available.Figure 2-42
For a given gate, tPHL = 0.05 ns and tPLH = 0.10 ns. Suppose that an inertial delay model is to be developed from this information for typical gate-delay behavior.(a) Assuming a positive output
The rejection time for inertial delays is required to be less than or equal to the propagation delay. In terms of the discussion of the example in Figure 2-25, why is this condition necessary to
Assume that tpd is the average of tPHL and tPLH. Find the delay from each input to the output in Figure 2-41 by(a) Finding tPHL and tPLH for each path, assuming tPHL = 0.20 ns and tPLH = 0.36 ns for
The waveform in Figure 2-40 is applied to an inverter. Find the output of the inverter, assuming that(a) It has no delay.(b) It has a transport delay of 0.06 ns.(c) It has an inertial delay of
The NOR gates in Figure 2-39 have propagation delay tpd = 0.073 ns and the inverter has a propagation delay tpd = 0.048 ns. What is the propagation delay of the longest path through the
Implement the following Boolean function with exclusive- OR and AND gates, using a minimum number of gate inputs:
Prove that the dual of the exclusive-OR is also its complement.
Optimize the following Boolean functions F together with the don’t-care conditions d in (1) sum-of-products and (2) product-of-sums form:
Optimize the following Boolean functions F together with the don’t-care conditions d. Find all prime implicants and essential prime implicants, and apply the selection rule.
Optimize the following Boolean functions F together with the don’ t-care conditions d:
Optimize the following functions into (1) sum-of-products and (2) product-of-sums forms:
Optimize the following expressions in (1) sum-of-products and (2) product-of-sums forms:
Optimize the following Boolean functions in product- of- sums form:
Optimize the following Boolean functions by inding all prime implicants and essential prime implicants and applying the selection rule:
Find all the prime implicants for the following Boolean functions, and determine which are essential:
Find the minterms of the following expressions by irst plotting each expression on a map:
Optimize the following Boolean functions, using a map:
Optimize the following Boolean functions by means of a 4-variable map:
Optimize the following Boolean expressions using a map:
Optimize the following Boolean functions by means of a 3-variable map:
Draw the logic diagram for the following Boolean expressions. The diagram should correspond exactly to the equation. Assume that the complements of the inputs are not available.
Convert the following expressions into sum- of- products and product-of-sums forms:
For the Boolean functions E and F, as given in the following truth table:
Obtain the truth table of the following functions, and express each function in sum-of-minterms and product- of- maxterms form:
Find the complement of the following expressions:
Using DeMorgan’s theorem, express the function(a) With onlyOR and complement operations.(b) With only AND and complement operations.(c) With only NAND and complement operations.
Reduce the following Boolean expressions to the indicated number of literals:
Simplify the following Boolean expressions to expressions containing a minimum number of literals:
speciic Boolean algebra with just two elements 0 and 1 has been used in this chapter. Other Boolean algebras can be deined with more than two elements by using elements that correspond to binary
Given that A • B = 0 and A + B = 1, use algebraic manipulation to prove that
Prove the identity of each of the following Boolean equations, using algebraic manipulation:
Prove the identity of each of the following Boolean equations, using algebraic manipulation:
Demonstrate by means of truth tables the validity of the following identities:
What is the percentage of power consumed for continuous counting (either up or down but not both) at the outputs of a binary Gray code counter (with all 2n code words used) compared to a binary

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