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engineering
electronic devices and circuit theory

Electronic Devices And Circuit Theory 11th Edition Robert Boylestad, Louis Nashelsky - Solutions

For the network of Fig. 7.83 , determine:a. ID.b. VDS.c. VD.d. VS. 20 V 2.2 k2 Ipss = 4.5 mA Vp = -5 V Vps 0.68 k2 -4 V FIG. 7.83
Find VS for the network of Fig. 7.84 . 20 V 2.2 k2 Ipss = 4.5 mA Vp =-5 V Vps 0.68 k2 -4 V FIG. 7.83
For the network of Fig. 7.86 , VD = 12 V. Determine:a. ID .b. VS and VDS .c. VG and VGS .d. VP. o 20 V 2.2 k2 910 k2 Ipss = 10 mA %3D Vp = -3.5 V Vose 110 k2 1.1 k2 FIG. 7.85
Determine the value of RS for the network of Fig. 7.87 to establish VD = 10 V.Fig. 7.87 16 V Rp2 2 kn 36 k2 oVp= 10 V Ipss= 12 mA Vp= -8 V R2 2 12 kn Rs FIG. 7.87
Given VDS = 4 V for the network of Fig. 7.89 , determine:a. ID .b. VD and VS.c. VGS . 20 V 3 k2 4 V Vas 1.2 k2 6+2 V FIG. 7.89
Determine VD and VGS for the network of Fig. 7.91 using the provided information. Vp 4 V 1,8 kn 1 kn 16 Vo VGs Ipss = 4 mA Vp=-6 V 3.6 kn 1.2 kn FIG. 7.91
For the self-bias configuration of Fig. 7.92 , determine:a. IDQ and VGSQ.b. VDS and VD. 14 V 1.2 k2 Ioss = 6 mA Vp=-4 V Vose 1 MQ 0.43 k2 FIG. 7.92
For the network of Fig. 7.94 , determine:a. IDQ.b. VGSQ and VDSQ.c. VD and VS .d. VDS. 9 22 V 1.2 k2 Vas m=4 V Vas ton)-7 V D (on) =5 mA I M2 Vpše %3D Vose 0.51 k2 FIG. 7.94
For the voltage-divider configuration of Fig. 7.95, determine:a. IDQ and VGSQ.b. VD and VSFig. 7.95 22 V 1.2 k2 Vas m) =4 V Vas (on) = 7 V Ip (on) = 5 mA I MO Vpse 0.51 k2 FIG. 7.94
For the network of Fig. 7.96 , determine:a. VG.b. VGSQ and IDQ.c. IE.d. IB.e. VD.f. VC.Fig. 7.96 o 20 V 1.1 ka 330 k2 oVe 91 ka B = 160 Vo oss =6 mA Vp =-6 V Va 18 ka 1.2 k2 FIG. 7.96
For the combination network of Fig. 7.97 , determine:a. VB and VG .b. VE.c. IE, IC, and ID .d. IB.e. VC, VS and VD .f. VCE .g. VDSFig. 7.97 o16 V 2.2 k2 40 k2 OVD VB.VG pss = 6 mA VDs Vp =-6 V Vs.Vclle IB VCE B = 100 10 k2 VE l lg 1.2 k2
What do the readings for each configuration of Fig. 7.98 suggest about the operation of the network?Fig. 7.98 16 V 2.2 k2 40 ka Va. VG oss = 6 mA Vps Vp = -6 V Vs.Vcle Vee B= 100 10 ka 1.2 k2 FIG. 7.97
The network of Fig. 7.100 is not operating properly. What is the specific cause for its failure?Fig. 7.100 o 20 V 2 k2 330 k2 o 14.4 V Ipss = 10 mA Vp = -6 V 75 kS2 1 k2 FIG. 7.100
For the cascade amplifier of Fig. 8.93, using JFETs with specifications IDSS = 12 mA, VP = -3 V, and gos = 25 mS, calculate the circuit input impedance (Zi) and output impedance (Zo).Fig. 8.93 +18 V 2.2 ks2 2.2 k 0.05 pF 0.1 µF 0.05 µF V 20 mV 10 M2 10 ΜΩ 390 12 50 uF 390 2 50 µF FIG. 8.93
Determine the regulated voltage and circuit currents for the shunt regulator of Fig. 15.45. Fig. 15.45 Vo V, + 33 2 (+15 V) 10 V RE 100 2 FIG. 15.45
Using the plot of Fig. 16.6a,a. What is the forward voltage at a current of 50 mA (note the log scale) at room temperature (25°C).b. What is the forward voltage at the same current as part (a) but a temperature of 125°C?c. What can be said about the effect of temperature on the resulting voltage
Describe in your own words the basic behavior of the SCR using the two-transistor equivalent circuit.
Describe two techniques for turning an SCR off.
In Fig. 17.10b , why is there very little loss in potential across the SCR during conduction? RL +A D VF - KO G IG (b)
Consult a manufacturer’s manual or specification sheet and obtain a turn-off network. If possible, describe the turn-off action of the design.
Fully explain why reduced values of R1 in Fig. 17.11 will result in an increased angle of conduction.Fig. 17.11 R1. R A R1 0° 90° 90° conduction K (a) (b)
Refer to the emergency-lighting system of Fig. 17.14.a. Sketch the waveform of the full-wave rectified signal across the bulb using a drop of 0.7 V during conduction of each diode.b. Determine the peak voltage across the capacitor C1 when the SCR 1 is off.c. What is the peak voltage across
Refer to the temperature controller of Fig. 17.13.a. Sketch the waveform of the full-wave rectified waveform across the SCR.b. What is the peak current through the heater when the SCR is “on” and has a short-circuit equivalent between anode and cathode? Assume each diode has a drop of 0.7 V
Fully describe in your own words the behavior of the networks of Fig. 17.16.Fig. 17.16 off >RL RL off off -V (a) (b) (c) ele
What is the suggested turn-off procedure for the network of Fig. 17.18?Fig. 17.18 o 12 V Alarm Input 1o Input 2 o W 10 k2 Input 30MW 10 ka 10 k2 FIG. 17.18 000, le
For the network of Fig. 17.19Fig. 17.19a. Write an equation for the voltage from gate to ground for the SCR.b. What is the voltage VGK when R S = R?c. Find RS to establish a turn-on voltage of 2 V if R' = 10 kΩ.d. When the alarm turns on, what is the current through the relay?e. At V A = 0 V,
a. In Fig. 17.22, if VZ = 50 V, determine the maximum possible value the capacitor C1 can charge to (VGK ≅ 0.7 V).b. Determine the approximate discharge time (5t) for R3 = 20 k.c. Determine the internal resistance of the GTO if the rise time is one-half the decay period determined in part
a. Using Fig. 17.24b, determine the minimum irradiance required to fire the device at room temperature (25°C).b. What percentage reduction in irradiance is allowable if the junction temperature is increased from 0°C (32°F) to 100°C (212°F)?Fig. 17.24b 40 20 10 Triggering region 0.8 0.6 No
For the network of Fig. 17.28, if VBR = 6 V, V = 40 V, R = 10 kΩ, C = 0.2 mF, and VGK (firing potential) = 3 V, determine the time period between energizing the network and the turning on of the SCR.Fig. 17.28 V R FIG. 17.28
Using whatever reference you require, find an application of a diac and explain the network behavior.
If VBR2 is 6.4 V, determine the range for VBR1 using Eq. (17.1).Eq. (17.1) VBR, = VBR, + 0.1VBR,
Find the level of human body capacitance Cb that would result in a 45-degree phase shift between vi and vG for the network of Fig. 17.30.Fig. 17.30 47 k2 10 MQ Load A G I MO То sensing electrode (115 V Vi 60 Hz) 1 MO DIAC PUT SCR K 1 k2 All resistors 1/4 W FIG. 17.30
For the network of Fig. 17.33, if C = 1μF, find the level of R that will result in a 50% conduction period for the load in either direction if the turn-on voltage for the diac in either direction is 12 V and the applied sinusoidal signal has a peak value of 170 V (= 1.414 × 120 V) at 60 Hz.Fig.
For the network of Fig. 17.40, in which V = 40 V, h = 0.6, VV = 1 V, IV = 8 mA, and IP = 10 mA, determine the range of R1 for the triggering network.Fig. 17.40 Load Ry E R2
For a phototransistor having the characteristics of Fig. 17.50, determine the photoinduced base current for a radiant flux density of 5 mW/cm2. If hfe = 40, find IC.Fig. 17.50 75 50 4 6 8 10 Radiation flux density H (mW/cm?) (a) e = 10° max. (d) (b) Base current IR (HA) 21
a. Determine an average derating factor from the curve of Fig. 17.58 for the region defined by temperatures between 25°C and50°C.b. Is it fair to say that for temperatures greater than room temperature (up to 100°C), the output current is somewhat unaffected by temperature?Fig. 17.58
Determine from Fig. 17.55 the ratio of LED output current to detector input current for an output current of 20 mA. Would you consider the device to be relatively efficient in its purpose?Fig. 17.55 30 25 20 15 10 5 O LED input current IF (mA) 10 20 30 40 50 60 Detector output current le (mA)
a. Sketch the maximum-power curve of PD = 200 mW on the graph of Fig. 17.56. List any noteworthy conclusions.b. Determine βdc (defined by IC/IF) for the system at VCE = 15 V, IF = 10 mA.c. Compare the results of part (b) with those obtained from Fig. 17.55 at IF = 10 mA. Do they compare?
Determine μ and VG for a PUT with VBB = 20 V and RB1 = 3RB2.
a. Repeat parts (a) through (e) of Problem 25 for the network of Fig. 4.128. Change b to 180 in part (b).Fig. 4.128b. What general conclusions can be made about networks in which the condition bRE > 10R2 is satisfied and the quantities IC and VCE are to be determined in response to a change in
a. Using the characteristics of Fig. 4.121, determine RC and RE for a voltage-divider network having a Q -point of ICQ = 5 mA and VCEQ = 8 V. Use VCC = 24 V and RC = 3RE.b. Find V E.c. Determine VB.d. Find R 2 if R1 = 24 kΩ assuming that bRE > 10R2.e. Calculate b at the Q -point.f. Test Eq.
Given the information provided in Fig. 4.124 , determine:a. b.b. V CC.c. R B. Ver 20 μΑ, 2.7 k 2 Ry Ver = 7.3 V 2.1 0.68 k2 FIG. 4.124
Given the information provided in Fig. 4.123 , determine:a. R C.b. R E.c. R B.d. VCE.e. VB. 12 V 2 mA RC RB o 7.6 V Va Vce B = 80 02.4 V RE FIG. 4.123
a. Draw the load line for the network of Fig. 4.122 on the characteristics of Fig. 4.121 using b from problem 8 to find IBQ.Fig. 4.122Fig. 4.121b. Find the Q -point and resulting values ICQ and VCEQ.c. Find the value of b at the Q -point.d. How does the value of part (c) compare with b 125 in
For the emitter-stabilized bias circuit of Fig. 4.122, determine:a. IBQ.b. ICQ.c. VCEQ.d. V C .e. V B .f. V EFig. 4.122 20 V 470 2 270 k2 oVc VB VCEQ B= 125 IBQ VE 2.2 k2
If the base resistor of Fig. 4.118 is increased to 910 k, find the new Q -point and resulting values of ICQ and VCEQFig. 4.118 16 V 1.8 kQ 510k2 Vc VCE. B=120 IBQ oVE FIG. 4.118
a. Ignoring the provided value of b(120) draw the load line for the network of Fig. 4.118 on the characteristics of Fig.4.121.Fig. 4.118Fig.4.121b. Find the Q -point and the resulting ICQ and VCEQ.c. What is the beta value at this Q -point? 16 V Ico 1.8 k2 510 k2 VCE B=120 oVE FIG. 4.118
a. Using the characteristics of Fig. 3.24 , determine b ac at IC = 14 mA and VCE = 3 V.b. Determine β dc at IC = 1 mA and VCE = 8 V.c. Determine β ac at IC = 14 mA and VCE = 3 V.d. Determine β dc at IC = 1 mA and VCE = 8 V.e. How does the level of b ac and b dc compare in each region?f. Is the
Using the characteristics of Fig. 3.23c , determine the level of b dc at IC = 10 mA at the three levels of temperature appearing in the figure. Is the change significant for the specified temperature range? Is it an element to be concerned about in the design process?Fig. 3.23 MAXIMUM
Using the information provided in Fig. 3.23 regarding PDmax, VCEmax, ICmax and VCEsat, sketch the boundaries of operation for the device.Fig. 3.23 Figure 5 – Frequency Variations 12 Source resistance = 200 2 Ic =1 mA 10 Source resistance = 200 2 Ic = 0.5 mA 8 Source resistance = 1 k2 Ic = 50µ
Determine the region of operation for a transistor having the characteristics of Fig. 3.8 if IC max = 7 mA, BV CBO = 20 V, and PC max = 42 mW.Fig. 3.8 4 c (mA) Active region (unshaded area) - 7 mA 7 6 mA 5 mA 5 4 mA 3 mA 3. 2 mA IE = 1 mA Ico=!CBO I=0 mA -1 10 20 30 40 VCB
Using the characteristics of Fig. 3.13a, determine βdc at I B = 25 mA and VCE = 10 V. Then calculate a dc and the resulting level of IE . (Use the level of IC determined by IC = bdcIB.)Fig. 3.13 lc (mA) 8. 90 μΑ 7 80 μΑ 70 μΑ 60 μΑ 50 μΑ (Saturation region) 5 40 µA 30
From memory only, sketch the common-emitter configuration (for npn and pnp ) and insert the proper biasing arrangement with the resulting current directions for IB, IC and IE.
a. Using the characteristics of Fig. 3.13a, determine b ac at I B = 60 mA and V CE = 4 V.b. Repeat part (a) at IB =30 μA and VCE =7 V.c. Repeat part (a) at IB = 10 μA and VCE = 10 V.d. Reviewing the results of parts (a) through (c), does the value of b ac change from point to point
a. Using the characteristics of Fig. 3.13a, determine b dc at IB = 60 mA and VCE = 4 V.Fig. 3.13ab. Repeat part (a) at IB = 30 μ A and VCE = 7 V.c. Repeat part (a) at IB = 10μ A and VCE =10 V.d. Reviewing the results of parts (a) through (c), does the value of b dc change from point to
a. Using the characteristics of Fig. 3.13a, determine I CEO at VCE = 10 V.b. Determine b dc at I B =10 mA and VCE = 10 V.c. Using the b dc determined in part (b), calculate ICBO. lc (mA) 90 μΑ 80 μΑ 70 μΑ 60 μΑ 1 IB (HA) VCE = 1 V VCE = 10 V 6. 100 (Saturation region) 5 50 μΑ VCE = 20
a. For the common-emitter characteristics of Fig. 3.13, find the dc beta at an operating point of VCE = 6 V and IC = 2 mA.b. Find the value of a corresponding to this operating point.c. At VCE = 6 V, find the corresponding value of I CEO.d. Calculate the approximate value of I CBO using the dc
Using the characteristics of Fig. 3.13:a. Find the value of IC corresponding to VBE =750 mV and VCE = 4 V.b. Find the value of VCE and V BE corresponding to IC = 3.5 mA and IB =30 mA. tle (mA) 90 LA 80 μΛ 70 uA 60 µA HA) 6. V = 10 V 100 (Saturation region) 50 μΑ Ver = 20
Define ICBO and ICEO . How are they different? How are they related? Are they typically close in magnitude?
From memory only, sketch the common-base BJT transistor configuration (for npn and pnp) and indicate the polarity of the applied bias and resulting current directions.
a. Given an ADC of 0.998, determine IC If IE = 4 mA.b. Determine a dc if I E = 2.8 mA, IC = From memory only, sketch the common-base BJT transistor configuration (for npn and pnp) and indicate the polarity of the applied bias and resulting current directions.2.75 mA and ICBO = 0.1 mA.
Perform a general analysis of the Zener network of Fig. 2.188 using PSpice Windows.Fig. 2.188 Rs 912 Vz = 8 V Pzma = 400 mWw R. 0.22 k2 FIG. 2.188 Problems 44 and 52.
Perform a PSpice Windows analysis of the network of Problem 1.Problem 1a. What is the expected amplification of a BJT transistor amplifier if the dc supply is set to zero volts?b. What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on the waveform.c. What is
Perform a Multisim analysis of the network of Problem 33.Problem 33For the network of Fig. 7.102 , determine:a. IDQ and VGSQ.b. VDS.c. VD.Fig. 7.102 9-16 V 2 k2 1 M2 Vas (h) = -3 V ID (on) = 4 mA Vas (om) =-7 V Vose FIG. 7.102
Perform a PSpice Windows analysis of the network of Problem 6.Problem 6a. Given an Early voltage of V A = 100 V, determiner o if VCEQ = 8 V and ICQ = 4 mA.b. Using the results of part (a), find the change in I C for a change in V CE of 6 V at the same Q -point as part (a).
Calculate gm0 for a JFET having device parameters IDSS = 12 mA and VP = -4 V.
A specification sheet provides the following data (at a listed drain-source current): 8fs = 4.5 mS, = 25 us %3!
Determine the pinch-off voltage of a JFET with gm0 = 10 mS and IDSS = 12 mA.
For a JFET having device parameters gm0 = 5 mS and VP = -4 V, what is the device current at VGS = 0 V?
If a JFET having a specified value of rd = 100 k has an ideal voltage gain of Av(FET) = -200 what is the value of gm? Alp (mA) 10 9. 8 6 1 -5 -4 -3 -2 -1 Vas (V)
Calculate the value of gm for a JFET (IDSS = 12 mA, VP = -3 V) at a bias point of VGS = -0.5 V.
A JFET (IDSS = 10 mA ,VP = -5 V) is biased at ID = IDSS>4. What is the value of g m at that bias point?
Determine the value of g m for a JFET (IDSS = 8 mA, VP = -5 V) when biased at VGSQ = VP/4.
a. Find the value of R S to obtain a voltage gain of 2 for the network of Fig. 8.74 using r d = ∞Ω.b. Repeat part (a) with r d =30 kΩ . What was the impact of the change in r d on the gain and the analysis? 16 V Rp2 2.7 kn Ipss = 9 mA Vp= -8 V I MN Rg FIG. 8.74
Repeat Problem 26 if rd = 20 kΩ and compare results.Problem 26Repeat Problem 25 with the capacitor C S removed and compare results.Problem 25Determine Zi , Zo , and Vo for the network of Fig. 8.76 if Vi = 20 mV.Fig. 8.76 +20 V 2 k2 82 ΜΩ o Vo Ipss = 12 mA Vp =-3 V ra= 50 k2 11 MQ R5 Cs 610
At the listed drain–source current, determine:a. gm.b. rd.
Repeat Problem 25 with the capacitor C S removed and compare results.Problem 25Determine Zi , Zo , and Vo for the network of Fig. 8.76 if Vi = 20 mV.Fig. 8.76 +20 V 2 k2 82 ΜΩ o Vo Ipss = 12 mA Vp =-3 V ra= 50 k2 11 MQ R5 Cs 610 Ω FIG. 8.76
For a 2N4220 n -channel JFET [gfs(minimum) = 750 μ S, gos(maximum) = 10 mS]:a. What is the value of gm ?b. What is the value of rd ?
Determine Zi, Zo, and Av for the network of Fig. 8.79.Fig. 8.79 +20 V Ipss=9 mA Vp= -4.5 V ra= 40 kQ 10 MQ A어 Z. 2.2 k2 FIG. 8.79
Repeat Problem 32 if rd = 20 kΩ and compare results.Problem 32 Determine Z i , Z o , and Av for the network of Fig. 8.79 .Fig. 8.79 +20 V Ipss=9 mA Vp= -4.5 V ra= 40 kQ 10 MQ A어 Z. 2.2 k2 FIG. 8.79
Repeat Problem 20 if g os is 10 μ S. Compare the results to those of Problem 20.Problem 20Determine Zi , Zo , and Av for the network of Fig. 8.73 if gfs = 3000 μS and gos = 50 μs.
Determine Vo for the network of Fig. 8.83 if Vi = 1.8 mV.Fig. 8.83 +18 V 6.8 k2 91 M2 . 8 = 35 µs Sos = 6000 uS 15 M2 3.3 k2 FIG. 8.83
Determine Zi , Zo , and Av for the network of Fig. 8.84.Fig. 8.84 +20 V Ipss = 12 mA Vp= -3 V la= 45 k2 91 ΜΩ V; c 10 ΜΩ 1.1 k2 FIG. 8.84
Determine Zi , Zo , and Av for the amplifier of Fig. 8.85 if k = 0.3 × 10-3.Fig. 8.85 +16 V 2.2 kΩ 10 ΜΩ VGSCTH) = 3 V ra= 100 k2 V
Determine Vo for the network of Fig. 8.86 if Vi = 4 mV, VGS(Th) = 4 V, and ID(on) = 4 mA, with VGS(on) = 7 V and gos = 20 mS. +20 V 10 kQ 22 M2 VGSCTH) = 3.5 V k= 0.3 x 10-3 8o 30 μS FIG. 8.86
Design the fixed-bias network of Fig. 8.88 to have a gain of 8.Fig. 8.88 +Vpp (+22 V) Rp Vo Ipss = 8 mA Vp =-2.5 V Yos = 20 µS 10 M2 FIG. 8.88
Determine g m for a MOSFET if VGS(Th) = 3 V and it is biased at VGSQ = 8 V. Assume k = 0.3 × 10-3.
Design the self-bias network of Fig. 8.89 to have a gain of 10. The device should be biased at VGSQ = 1/3 VP. +Vpp (+20 V) Rp Ipss = 12 mA Vp =-3 V r= 40 k2 V,oH 10 MQ Rs FIG. 8.89
For the source-follower network of Fig. 8.91 :a. Determine AvNL, Zi, and Zo.b. Sketch the two-port model of Fig. 5.75 with the parameters determined in part (a) in place.c. Determine AvL and Avs.d. Change R L to 4.7 kΩ and calculate AvL and Avs. What was the effect of increasing levels of RL on
For the common-gate configuration of Fig. 8.92 :a. Determine AvNL, Zi and Zo.b. Sketch the two-port model of Fig. 5.75 with the parameters determined in part (a) in place.c. Determine AvL and Avs.d. Change RL to 2.2 kΩ and calculate AvL and Avs. What was the effect of changing RL on the voltage
For the JFET cascade amplifier in Fig. 8.93 , calculate the dc bias conditions for the two identical stages, using JFETs with IDSS = 8 mA and VP = -4.5 V. +18 V 2.2 k2 2.2 k2 0.05 µF 0.1 µF 0.05 µF Q2 20 mV 10 M2 10 MQ 390 2 50 µF 390 2 50 µF FIG. 8.93
If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having specifications IDSS = 12 mA and VP = -3 V, calculate the resulting dc bias of each stage.Fig. 8.93 +18 V 2.2 k2 2.2 k2 0.05 µF 0.1 µF 0.05 µF V 20 mV 10 M2 10 MQ 390 2 50 uF 390 2 50 µF FIG. 8.93
For the cascade amplifier of Fig. 8.94, calculate the dc bias voltages currents of each stage.Fig. 8.94 +10 V 1.8 k2 24 k2 2.7 k2 0.1 µF 0.05 µF IDss = 6 mA Vp = -3 V V; = B = 150 2 mV 10 MQ 8.2 k2 330 2 100 μF 2.2 k2 100 µF FIG. 8.94
If both JFETs in the cascade amplifier of Fig. 8.93 are changed to those having the specifications IDSS = 12 mA, VP = -3 V, and gos = 25 mS, calculate the resulting voltage gain for each stage, the overall voltage gain, and the output voltage,Fig. 8.93 +18 V 2.2 ks2 2.2 k 0.05 pF 0.1 µF 0.05
Calculate the input impedance (Zi) and output impedance (Zo) for the amplifier circuit of Fig. 8.94.Fig. 8.94 +10 V 1.8 k2 24 k2 2.7 kn 0.1 µF 0.05 µF IDSS = 6 mA Vp = -3 V V; = o B = 150 2 mV 10 M2 8.2 ΚΩ 330 2 100 μF 2.2 k2 100 με FIG. 8.94
Using PSpice Windows, determine the voltage gain for the network of Fig. 8.76.Fig. 8.76 +20 V 2 k2 82 M2 o Vo Ipss = 12 mA Vp =-3 V ra= 50 k2 11 MQ Rs Cs 610 Ω FIG. 8.76
Using Multisim, determine the voltage gain for the network o Fig. 8.77.Fig. 8.77 +15 V 3.3 k2 Ipss = 8 mA Vp=-2.8 V ra= 40 k2 Zo 1.5 k2 FIG. 8.77
Use the Design Center to draw a schematic circuit of the cascade JFET amplifier as in Fig.8.93. Set the JFET parameters for IDSS = 12 mA and VP = 3V, and have the analysis determine the dc bias.Fig.8.93 +18 V 2.2 k2 2.2 k 0.05 µF 0.1 µF 0.05 µF 20 mV 10 M2 10 M2 390 2. 50 µF 50
Use the Design Center to draw a schematic circuit for a cascade JFET amplifier as shown in Fig. 8.93 . Set the analysis to calculate the ac output voltage Vo for IDSS = 12 mA and VP = 3V.Fig. 8.93 +18 V 2.2 k2 2.2 k 0.05 µF 0.1 µF 0.05 µF Vị 20 mV 10 M2 10 M2 50 pF 50 µF 390 12 390 2 FIG. 8.93
Determine:a. 20 log10 using Eq. (9.6) and compare with 20 log10 × 14.b. 10 log10 using Eq. (9.7) and compare with 10log10 4 × 10-3.c. log10 (40)(0.2) using Eq. (9.8) and compare with log108. 84

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