Given the following MIPS assembly like code:

$[0]$

Li R$8,8$

L: $,$ LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

Sub $R7,R1,R3$

LW R$4,10($R$7)$

SW R$4,20($R$1)$

Subi R$8,$ R$8,4$

BNEQZ R$8,L$

Also, given the following latencies for each stage:

IF: $80ns,$ ID: $30ns,$ EX: $50ns,$ MEM: $85ns,$ and WB: $35ns$

What is the total number of stall cycles needed when running this code on a MIPS Pipelined CPU without data forwarding and the branch resolved in the EX Stage and initialized to be Not Taken. Ignore initial pipeline fill cycles.

A$.20$

B$.24$

C$.10$

D$.12$

E$.22$