Given the following MIPS assembly like code: $8$ L : Lw R$2$R$3,$ R$7$ Add R$2$R$3$ Sub R$7$ R$3$ R$410($R$7)$ Sw R$420($R$1)$ Subi $4$ BNEQZ L Also, given the following latencies for each stage: IF: $80$nsID: $30$ns$,$ EX : $50$nsMEM: $85$ns$,$ and WB: $35$ns What is the total number of cycles needed when running this code on ideal MIPS Pipelined CPU $?$ A$.20$ None of the answers $15$ D$.1916$