Given the following MIPS assembly like code:

LiR $8,8$

L: $,$ LW R$2,$ R$3,$ R$7$

Add R$1,$ R$2,$ R$3$

SUb R$7,$ R$1,$ R$3$

LW R$4,10($R$7)$

SW R$4,2$O$($RI$)$

Subi R$8,$ R$8,4$

BNEQZ.R$8,$ L

Also, given the following latencies for each stage:

IF: $80ns,$ ID: $30ns,$ EX: $50ns,$ MEM: $85ns,$ and WB: $35ns$

What is the total number of cycles needed when running this code on

ideal MIPS Pipelined CPU?

A$.19$

$16$

C$.15$

D$.$ None of the answers

E$.20$