Question: Given the rollowing MIPS assembly like code: Li R 8 , 8 LW R 2 , R 3 , R 7 Add R 1 ,
Given the rollowing MIPS assembly like code:
Li R
LW R R R
Add R R R
Sub
LW RR
SW RR
Subi R R
BNEQZ R L
Also, given the following latencies for each stage:
IF: ns ID: ns EX: ns MEM: s and WB:
What is the total number of cycles needed when running this code on a MIPS Pipelined CPU
with the using of full data forwarding and the pranch resolved in the ID Stage and initialized
to be Iaken. Ignore initial pipeline, fill cycles.Also, given the following latencies for each stage:
IF: s ID: ns EX: s MEM: and WB: ns
What is the total number of cycles needed when running this code on a MIPS Pipelined CPU
with the using of full data forwarding and the branch resolved in the ID Stage and initialized
to be Taken. Ignore initial pipeline fill cycles.
A
B
C
D
E
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