Computer Organization 5th Edition V Carl Hamacher, Carl Hamacher, Zvonko G Vranesic, Safwat G Zaky - Solutions

Consider the following sequence of instructionsIn all instructions, the destination operand is given last. Initially, registers RO and R2 contain 2000 and 50, respectively. These instructions are executed in a computer that has a four-stage pipeline similar to that shown in Figure 8.2. Assume that
Repeat Problem 8.1 for the following program:LO1 Add #20,R0,R1 Mul #3,R2,R3 And #$3A,R1,R4 Add RO,R2,R5
Instruction 12 in Figure 8.6 is delayed because it depends on the results of I. By occupying the Decode stage, instruction I2 blocks I3, which, in turn, blocks I4. Assuming that I3 and 14 do not depend on either I, or I2 and that the register file allows two Write steps to proceed in parallel, how
The delay bubble in Figure 8.6 arises because instruction I2 is delayed in the Decode stage. As a result, instructions I3 and I are delayed even if they do not depend on either I or 12. Assume that the Decode stage allows two Decode steps to proceed in parallel. Show that the delay bubble can be
Figure 8.4 shows an instruction being delayed as a result of a cache miss. Redraw this figure for the hardware organization of Figure 8.10. Assume that the instruction queue can hold up to four instructions and that the instruction fetch unit reads two instructions at a time from the cache.LO1
A program loop ends with a conditional branch to the beginning of the loop. How would you implement this loop on a pipelined computer that uses delayed branching with one delay slot? Under what conditions would you be able to put a useful instruction in the delay slot?LO1
The branch instruction of the UltraSPARC II processor has an Annul bit. When set by the compiler, the instruction in the delay slot is discarded if the branch is not taken. An alternative choice is to have the instruction discarded if the branch is taken. When is each of these choices
A computer has one delay slot. The instruction in this slot is always executed, but only on a speculative basis. If a branch does not take place, the results of that instruction are discarded. Suggest a way to implement program loops efficiently on this computer.LO1
Rewrite the sort routine shown in Figure 2.34 for the SPARC processor. Recall that the SPARC architecture has one delay slot with an associated Annul bit and uses branch prediction. Attempt to fill the delay slots with useful instructions wherever possible.LO1
Consider a statement of the formWrite a sequence of assembly language instructions, first using branch instructions only, then using conditional instructions such as those available on the ARM processor. Assume a simple two-stage pipeline, and draw a diagram similar to that in Figure 8.8 to compare
The feed-forward path in Figure 8.7 (blue lines) allows the content of the RSLT register to be used directly in an ALU operation. The result of that operation is stored back in the RSLT register, replacing its previous contents. What type of register is needed to make such an operation possible?
Write the program in Figure 2.37 for a processor in which only load and store in- structions access memory. Identify all dependencies in the program and show how you would optimize it for execution on a pipelined processor.LO1
Assume that 20 percent of the dynamic count of the instructions executed on a computer are branch instructions. Delayed branching is used, with one delay slot. Estimate the gain in performance if the compiler is able to use 85 percent of the delay slots.LO1
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots 85 percent of the time and can fill the second slot only 20 percent of the time. What is the percentage improvement in performance achieved by this optimization, assuming that 20 percent of the
A pipelined processor uses the delayed branch technique. You are asked to recommend one of two possibilities for the design of this processor. In the first possibility, the processor has a 4-stage pipeline and one delay slot, and in the second possibility, it has a 6-stage pipeline with two delay
Consider a processor that uses the branch prediction mechanism represented in Fig- ure 8.15b. The initial state is either LT or LNT, depending on information provided in the branch instruction. Discuss how the compiler should handle the branch instructions used to control "do while" and "do until"
Assume that the instruction queue in Figure 8.10 can hold up to six instructions. Redraw Figure 8.11 assuming that the queue is full in clock cycle 1 and that the fetch unit can read up to two instructions at a time from the cache. When will the queue become full again after instruction I is
Redraw Figure 8.11 for the case of the mispredicted branch in Figure 8.14.LO1
Figure 8.16 shows that one instruction that uses a complex addressing mode takes the same time to execute as an equivalent sequence of instructions that use simpler addressing modes. Yet, the use of simple addressing modes is one of the tenets of the RISC philosophy. How would you design a pipeline
The microcontroller in Section 9.3 receives decimal digits (0 to 9) encoded as ASCII characters on its serial port. As each digit arrives, it has to be displayed on a 7-segment display unit connected to parallel Port A. Show the connections needed to accomplish this function. Label the segments of
Write an assembly language program to implement the task of Problem 9.1.
Solve Problem 9.1 by using interrupts to detect the arrival of each ASCII character.LO1
Write an assembly language program for Problem 9.3.LO1
The microcontroller in Section 9.3 receives decimal numbers on its serial port. Each number consists of two digits encoded as ASCII characters. In order to distinguish between successive 2-digit numbers, a delimiter character H is used. Thus, if two successive numbers are 43 and 28, the received
Write an assembly language program to implement the task of Problem 9.5.LO1
Solve Problem 9.5 by using interrupts to detect the arrival of each ASCII character.LO1
Write an assembly language program for Problem 9.7.LO1
The microcontroller in Section 9.3 receives decimal numbers on its serial port. Each number consists of four digits encoded as ASCII characters. In order to distinguish between successive 4-digit numbers, a delimiter character H is used. Thus, if two suc- cessive numbers are 2143 and 6292, the
Write an assembly language program to implement the task of Problem 9.9.LO1
Solve Problem 9.9 by using interrupts to detect the arrival of each ASCII character.LO1
Write an assembly language program to implement the task of Problem 9.11.LO1
Repeat Problem 9.9, but assume that each 7-segment display unit has a 7-bit register associated with it, rather than a BCD-to-7-segment decoder. The register has a control input Load, such that the seven data bits are loaded into the register when Load = 1. Each bit in the register drives one
Repeat Problem 9.13, but write the program using assembly language.LO1
Solve Problem 9.13 by using interrupts to detect the arrival of each ASCII character.LO1
Write an assembly language program to implement the task of Problem 9.15.LO1
In Section 9.5 we assumed that the source device generates characters in bursts of less than 80 characters. Would the programs in Figures 9.17 and 9.18 work properly if bursts of up to 80 characters are allowed? If not, show a modification to these programs.LO1
In the program in Figure 9.17, the test for determining whether the circular buffer is empty is performed by checking if the fin and fout indexes have the same value. Instead, it is possible to introduce a counter variable, M, that indicates the current number of characters in the buffer. Modify
Repeat Problem 9.18 for the program in Figure 9.18.LO1
Modify the reaction timer presented in Section 9.6 assuming that the tested person will always respond in less than one second. Thus, the elapsed reaction time should be displayed as two digits representing the hundredths of a second. Connect the two 7-segment display units to Port A and modify the
In Figure 9.19, the 7-segment display unit for each digit incorporates a BCD-to-7- segment decoder; hence the microcontroller provides simultaneously a 4-bit BCD code for each digit that is to be displayed. Suppose that instead of using the decoder, each 7-segment unit has a 7-bit register with a
In Figure 9.21, a binary number representing the elapsed reaction time in hundredths of seconds is converted into an equivalent BCD number using successive divisions by 100 and 10. Another way of implementing this conversion is to perform successive divisions by 10, in which case the remainder
Use the microcontroller in Section 9.3 to generate a "time of day" clock. The time (in hours and minutes) is to be displayed on four 7-segment display units. Assume that each display unit has a BCD-to-7-segment decoder associated with it, as shown in Figure P9.1. Assume also that a 100-MHz clock is
Repeat Problem 9.20 assuming that each 7-segment display unit has a register associated with it, as shown in Figure P9.2.LO1
In a system implemented on a single chip, the processor and the main memory reside on the same chip. Is there a need for a cache in this system? Explain.LO1
The display on a video screen must be refreshed at least 30 times per second to remain flicker-free. During each full scan of the screen, the total time required to illuminate each point is 1 us. The beam is then turned off and moved to the next point to be illuminated. On average, moving the beam
Consider a communication channel that uses eight-valued signals instead of the two- valued signals used in a binary channel. If the channel is rated at 9600 baud, what is its capacity in bits per second?LO1
The following components are provided: A 6-bit binary counter, with Clock and Clear inputs and six outputs A 3-bit serial-input-parallel-output shift register A clock running at eight times the input data rate Logic gates and D flip-flops with Preset and Clear controls Design a circuit using these
An asynchronous link between two computers uses the start-stop scheme, with one start bit and one stop bit, and a transmission rate or 38.8 kilobits/s. What is the effective transmission rate as seen by the two computers?LO1
A communication link uses odd parity for each character transmitted. Refer to Appendix E, and give the 8-bit pattern transmitted for the characters A, P, =, and 5.LO1
Consider a communication line modem connected to a computer through an RS-232-C interface. The control signals associated with this interface are accessed by the computer through a 16-bit register, as shown in Figure P10.1. The status change bit, bis, is set to 1 whenever there is a change in the
Assume the following register and memory contents in an ARM computer:The numbers 1, 2, 3, 4, 5, and 6, are stored in successive word locations starting at memory address 1000. What is the effect of executing each of the following three short instruction blocks, starting each time from the given
Which of the following ARM instructions would cause the assembler to issue a syntax error message? Why? (a) ADD R2,R2,R2 (b) SUB RO,R1,[R2,#4] (c) MOV R0,#2_1010101 (d) MOV R0,#257 (e) ADD RO,R1,R11,LSL #8
When a byte is loaded from memory into an ARM processor register using the Load instruction, the high-order 24 bits are cleared to Os. (See Section 3.1.2.) If the loaded byte represents an 8-bit signed integer in 2's-complement representation, it must be sign-extended to 32 bits in the register
Write an ARM program to reverse the order of bits in register R2. For example, if the starting pattern in R2 is 1110... 0100, the result left in R2 should be 0010... 0111. (Hint: Use shift and rotate operations.)
A program trace is a listing of the contents of certain registers and memory locations at different times during the execution of a program. List the contents of registers RO, R1, and R2 after each of the first three executions of the BGT instruction in the program in Figure 3.7. Present the
Write an ARM program that compares the corresponding bytes of two lists of bytes and places the larger byte in a third list. The two lists start at byte locations X and Y, and the larger-byte list starts at LARGER. The length of the lists is stored in memory location N.
An ARM program is required for the following character manipulation task: A string of n characters is stored in the memory in consecutive byte locations, beginning at location STRING. Another shorter string of m characters is stored in consecutive byte locations, beginning at location SUBSTRING.
Write an ARM program that generates the first n numbers of the Fibonacci series. In this series, the first two numbers are 0 and 1, and each subsequent number is generated by adding the preceding two numbers. For example, for n = 8, the series is 0,1,1,2,3,5,8,13 Your program should store the
Write an ARM program to convert a word of text from lowercase to uppercase. The word consists of ASCII characters stored in successive byte locations in the memory, starting at location WORD and ending with a space character. (See Appendix E for the ASCII code.)
The list of student marks shown in Figure 2.14 is changed to contain j test scores for each student. Assume that there are n students. Write an ARM program for computing the sums of the scores on each test and store these sums in the memory word locations at addresses SUM, SUM +4, SUM +8,.... The
Consider an array of numbers A(i,j), where i = 0 through n-1 is the row index and j = 0 through m-1 is the column index. The array is stored in the memory of an ARM computer one row after another, with elements of each row occupying m successive word locations. Write an ARM subroutine for adding
Write an ARM program that reads n characters from a keyboard and echoes them back to a display after pushing them onto a user stack as they are read. Use register R6 as the stack pointer. The count value n is contained in memory word location N.
Assume that the average time taken to fetch and execute an instruction in the program in Figure 3.9 is 20 nanoseconds. If keyboard characters are entered at the rate of 10 per second, approximately how many times is the BEQ READ in- struction executed per character entered? Assume that the time
In the ARM program in Figure 3.9, "in-line" code is used to read a line of characters and display them. Rewrite this program in the form of a main program that calls a subroutine named GETCHAR to read a single character and calls another subroutine named PUTCHAR to display a single character. The
Repeat Problem 3.14 using the stack to pass parameters.LO1
Write an ARM program to accept three decimal digits from a keyboard. Each digit is represented in the ASCII code (see Appendix E). Assume that these three dig- its represent a decimal integer in the range 0 to 999 and convert the integer into a binary number representation. The high-order digit is
The decimal-to-binary conversion program of Problem 3.16 is to be implemented us- ing two nested subroutines. The main program that calls the first subroutine passes two parameters by pushing them onto the stack whose pointer register is R13. The first parameter is the address of a 3-byte memory
Consider the queue structure described in Problem 2.18. Write ARM APPEND and REMOVE routines that transfer data between a processor register and the queue. Be careful to inspect and update the state of the queue and the pointers each time an operation is attempted and performed.
Using the format for presenting results that is described in Problem 3.5, give a program trace for the byte-sorting program in Figure 3.15b. Show the contents of registers RO, R2, and R3, and list byte locations LIST, LIST+1,..., LIST +4 for a 5-byte list after each execution of the last
Rewrite the byte-sorting program in Figure 3.15b as a subroutine that sorts a list of 32-bit positive integers. The calling program should pass the list address to the sub- routine. The first 32-bit quantity at that location is the number of entries in the list, followed by the numbers to be sorted.
Consider the byte-sorting program of Figure 3.15b. During each pass through a sublist, LIST(j) through LIST(0), list entries are swapped whenever LIST(k) > LIST(j). An alternative strategy is to keep track of the address of the largest value in the sublist and to perform, at most, one swap at the
Assume that the list of student test scores shown in Figure 2.14 is stored in the memory as a linked list as shown in Figure 2.36. Write an ARM program that accomplishes the same thing as the program in Figure 2.15. The head record is stored at memory location 1000.
The linked-list insertion subroutine in Figure 3.16 does not check if the ID of the new record matches that of a record already in the list. What happens in the execution of the subroutine if this is the case? Modify the subroutine to return the address of the matching record in register R10 if
The linked-list deletion subroutine in Figure 3.17 assumes that a record with the ID contained in register RIDNUM is in the list. What happens in the execution of the subroutine if there is no record with this ID? Modify the subroutine to return a zero in RIDNUM if deletion is successful, or leave
Consider the following state of the 68000 processor:What is the effect of executing each of the following three instructions, starting each time from this initial state? How many bytes does each instruction occupy? How many memory accesses does the fetching and execution of each instruction
Find the syntax errors in the following 68000 instructions: (a) ADDX (b) LSR.L (c) MOVE.B (d) SUBA.L (e) CMP.B -(A2),D3 #9,D2 520(A2,D2) 12(A2,PC),A0 #254,$12(A2,D1.B)
A program trace is a listing of the contents of certain registers and memory locations at different times during the execution of a program. List the contents of registers DO, DI, and A2 and memory locations N, NUM1, and SUM after each of five executions of the ADD. W instruction and after
Consider the following 68000 program:(a) What does this program do? (b) How many 16-bit words are needed to store this program in the memory? (c) Give an expression for the number of memory accesses required. The expression should be of the form T = a + bn + cm, where n is the number of times the
Consider the two 68000 programs given in Figure P3.1. (a) Do these programs leave the same value in location RSLT? (b) What task(s) do they accomplish?(c) How many bytes of memory are needed to store each program? (d) Which program requires the larger number of memory accesses? (e) What are the
Write a 68000 program that compares the corresponding bytes of two lists of bytes and places the larger byte in a third list. The two lists start at byte locations X and Y, and the larger-byte list starts at LARGER. The length of the lists is stored in memory loca- tion N.
A 68000 program is required for the following character manipulation task: A string of n characters is stored in the memory in consecutive byte locations, beginning at location STRING. Another, shorter string of m characters is stored in consecutive byte locations, beginning at location SUBSTRING.
Write a 68000 program that generates the first n numbers of the Fibonacci series. In this series, the first two numbers are 0 and 1, and each subsequent number is generated by adding the preceding two numbers. For example, for n = 8, the series is 0, 1, 1, 2, 3, 5, 8, 13 Your program should store
Write a 68000 program to convert a word of text from lowercase to uppercase. The word consists of ASCII characters stored in successive byte locations in the memory, starting at location WORD and ending with a space character. (See Appendix E for the ASCII code.)
The list of student marks shown in Figure 2.14 is changed to contain j test scores for each student. Each entry in the list is a 16-bit word, so the increments on LIST are by 2. Assume that there are n students. Write a 68000 program for computing the sums of the scores on each test and store these
Write a 68000 program that reads n characters from a keyboard and echoes them back to a display after pushing them onto a user stack as they are read. Use register AO as the stack pointer. The count value n is stored in memory word location N.
Assume that the average time taken to fetch and execute an instruction in the program in Figure 3.27 is 20 nanoseconds. If keyboard characters are entered at the rate of 10 per second, approximately how many times is the BEQ READ instruction executed per character entered? Assume that the time
In the 68000 program in Figure 3.27, "in-line" code is used to read a line of characters and display them. Rewrite this program in the form of a main program that calls a subroutine named GETCHAR to read a single character and calls another subroutine named PUTCHAR to display a single character.
Repeat problem 3.37 using the stack to pass parameters.LO1
Consider the queue structure described in Problem 2.18. Write 68000 APPEND and REMOVE routines that transfer data between a processor register and the queue. Be careful to inspect and update the state of the queue and the pointers each time an operation is attempted and performed.
Write a 68000 program to accept three decimal digits from a keyboard. Each digit is represented in the ASCII code (see Appendix E). Assume that these three digits represent a decimal integer in the range 0 to 999 and convert the integer into a binary number representation. The high-order digit is
The decimal-to-binary conversion program of Problem 3.40 is to be implemented as two nested subroutines. The main program that calls the first subroutine passes two parameters by pushing them onto the processor stack. The first parameter is the ad- dress of a 3-byte memory buffer area for storing
Consider an array of 16-bit numbers A(i,j), where i = 0 through n - 1 is the row index and j = 0 through m - 1 is the column index. The array is stored in the memory of a 68000 computer one row after another, with elements of each row occupying m successive word locations. Write a 68000 subroutine
Write a 68000 program to reverse the order of bits in register D2. For example, if the starting pattern in D2 is 1110...0100, the result left in D2 should be 0010... 0111. (Hint: Use shift and rotate operations.)
How many bytes of memory are needed to store the program in Figure 3.32? How many memory accesses take place during execution of this program?
Using the format for presenting results that is described in Problem 3.27, give a program trace for the byte-sorting program in Figure 3.34b. Show the contents of registers D1, D2, and D3, and the list byte locations LIST, LIST+1,..., LIST + 4 for a 5-byte list after each execution of the last
Rewrite the byte-sorting program in Figure 3.34b as a subroutine that sorts a list of 16-bit positive integers. The calling program should pass the list address to the sub- routine. The first 16-bit quantity at that location is the number of entries in the list, followed by the numbers to be sorted.
Consider the byte-sorting program of Figure 3.34b. During each pass through a sublist, LIST(j) through LIST(0), list entries are swapped whenever LIST(k) > LIST(j). An alternative strategy is to keep track of the address of the largest value in the sublist and to perform, at most, one swap at the
Assume that the list of student test scores shown in Figure 2.14 is stored in the memory as a linked list as shown in Figure 2.36. Write a 68000 program that accomplishes the same thing as the program in Figure 2.15. The head record is stored at memory location 1000. Assume that all list entries
The linked-list insertion subroutine in Figure 3.35 does not check if the ID of the new record matches that of a record already in the list. What happens in the execution of the subroutine if this is the case? Modify the subroutine to return the address of the matching record in register A6 if this
The linked-list deletion subroutine in Figure 3.36 assumes that a record with the ID con- tained in register RIDNUM is in the list. What happens in the execution of the subroutine if there is no record with this ID? Modify the subroutine to return a zero in RIDNUM if deletion is successful, or

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Computer Organization 5th Edition V Carl Hamacher, Carl Hamacher, Zvonko G Vranesic, Safwat G Zaky - Solutions

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