Questions and Answers of Computer System Architecture

Consider the instruction formats of the basic computer shown in Fig. 5-5 and the list of instructions given in Table 5-2. For each of the following 16-bit instructions, give the equivalent four-digit
Draw a timing diagram similar to Fig. 5-7 assuming that SC is cleared to 0 at time T3 if control signal C7 is active. C7T3: SC←0 C7 is activated with the positive clock transition
Assume that the first six memory-reference instructions in the basic computer listed in Table 5-4 are to be changed to the instructions specified in the following table. EA is the effective address
An instruction at address 021 in the basic computer has I = 0, an operation code of the AND instruction, and an address part equal to 083 (all numbers are in hexadecimal). The memory word at address
Show the contents in hexadecimal of registers PC, AR, DR, IR, and SC of the basic computer when an ISZ indirect instruction is fetched from memory and executed. The initial content of PC is 7FF. The
The content of PC in the basic computer is 3AF (all numbers are in hexadecimal). The content of AC is 7EC3. The content of memory at address 3AF is 932E. The content of memory at address 32E is 09AC.
The memory unit of the basic computer shown in Fig. 5-3 is to be changed to a 65,536 x 16 memory, requiring an address of 16 bits. The instruction format of a memory-reference instruction shown in
A computer uses a memory of 65,536 words with eight bits in each word. It has the following registers: PC, AR, TR (16 bits each), and AC, DR, IR (eight bits each). A memory-reference instruction
Make the following changes to the basic computer. 1. Add a register to the bus system CTR (count register) to be selected with S2S1S0 = 000. 2. Replace the ISZ instruction with an instruction that
The register transfer statements for a register R and the memory in a computer are as follows (the X's are control functions that occur at random):X'3X1: R←M[AR] Read memory word
A digital computer has a memory unit with a capacity of 16,384 words, 40 bits per word. The instruction code format consists of six bits for the operation part and 14 bits for the address part (no
An output program resides in memory starting from address 2300. It is executed after the computer recognizes an interrupt when FGO becomes a 1 (while IEN = 1). a. What instruction must be placed at
The operations to be performed with a flip-flop F (not used in the basic computer) are specified by the following register transfer statements:xT3: F←1 Set F to 1yT1: F←0
Derive the control gates associated with the program counter PC in the basic computer.
Derive the Boolean logic expression for x (see Table 5-7). Show that x2 can be generated with one AND gate and one OR gate.Table 5-7 0 1 0 0 0 00000000 TABLE 5-7 Encoder for Bus Selection Circuit X2
Derive the control gates for the write input of the memory in the basic computer.
Derive the Boolean expression for the gate structure that clears the sequence counter SC to 0. Draw the logic diagram of the gates and show how the output is connected to the INR and CLR inputs of SC
Show the complete logic of the interrupt flip-flops R in the basic computer. Use a JK flip-flop and minimize the number of gates.
The following program is stored in the memory unit of the basic computer. Show the contents of the AC, PC, and IR (in hexadecimal), at the end, after each instruction is executed. All numbers listed
The following program is a list of instructions in hexadecimal code. The computer executes the instructions starting from address 100. What are the content of AC and the memory word at address 103
What happens during the first pass of the assembler (Fig. 6-1) if the line of code that has a pseudoinstruction ORG or END also has a label? Modify the flowchart to include an error message if this
List the assembly language program (of the equivalent binary instructions) generated by a compiler from the following Fortran program. Assume integer variables.SUM = 0 SUM = SUM + A + B DIF = DIF -
a. Obtain the address symbol table generated for the program of Table 6-13 during the first pass of the assembler. b. List the translated program in hexadecimal.Table 6-13 Line 1 2 3 4 5 56 6 7 8 10
Can the letter I be used as a symbolic address in the assembly language program defined for the basic computer? Justify the answer.
Modify the flowchart of Fig. 6-2 to include an error message when a symbolic address is not defined by a label.Fig. 6-2 Set first bit to 1 Get operation code and set bits 2-4 Search address- symbol
A line of code in an assembly language program is as follows: DEC - 35a. Show that four memory words are required to store the line of code and give their binary content. b: Show that one memory
The pseudoinstruction BSS N (block started by symbol) is sometimes employed to reserve N memory words for a group of operands. For example, the line of code A, BSS 10 informs the assembler. that a
a. Explain in words what the following program accomplishes when it is executed. What is the value of location CTR when the computer halts? b. List the address symbol table obtained during the first
Show how the MRI and non-MRI tables can be stored in memory.
The multiplication program of Table 6-14 is not initialized. After the program is executed once, location CTR will be left with zero. Show that if the program is executed again starting from location
List the assembly language program (of the equivalent binary instructions) generated by a compiler for the following IF statement: IF (A - B) 10, 20, 30 The program branches to statement 10 if A -
Write a program loop, using a pointer and a counter, that clears to 0 the contents of hexadecimal locations 500 through 5FF.
Write a program to multiply two positive numbers by a repeated addition method. For example, to multiply 5 x 4, the program evaluates the product by adding 5 four times, or 5 + 5 + 5 + 5.
Write a program to multiply two unsigned positive numbers, each with 16 significant bits, to produce an unsigned double-precision product.
Write a program to multiply two signed numbers with negative numbers being initially in signed-2's complement representation. The product should be single-precision and signed-2's complement
Write a program to subtract two double-precision numbers.
Write a program that evaluates the logic exclusive-OR of two logic operands.
Write a program for the arithmetic shift-left operation. Branch to OVF if an overflow occurs.
Translate the service routine SRV from Table 6-23 to its equivalent hexadecimal code. Assume that the routine is stored starting from location 200.Table 6-23
Write a subroutine to subtract two numbers. In the calling program, the BSA instruction is followed by the subtrahend and minuend. The difference is returned to the main program in the third location
Write a subroutine to complement each word in a block of data. In the calling program, the BSA instruction is followed by two parameters: the starting address of the block and the number of words in
Write a subroutine to circulate E and AC four times to the right. If AC contains hexadecimal 079C and E= 1, what are the contents of AC and E after the subroutine is executed?
Write a program to accept input characters, pack two characters in one word and store them in consecutive locations in a memory buffer. The first address of the buffer is (400)16. The size of the
Write an interrupt service routine that performs all the required functions but the input device is serviced only if a special location, MOD, contains all 1's. The output device is serviced only if
What is the difference between a microprocessor and a microprogram? Is it possible to design a microprocessor without a microprogram? Are all microprogrammed computers also microprocessors?
The system shown in Fig. 7-2 uses a control memory of 1024 words of 32 bits each. The microinstruction has three fields as shown in the diagram. The microoperations field has 16 bits. a. How many
Explain the difference between hardwired control and microprogrammed control. Is it possible to have a hardwired control associated with a control memory?
The microprogrammed control organization shown in Fig. 7-1 has the following propagation delay times. 40 ns to generate the next address, 10 ns to transfer the address into the control address
Define the following: (a) Microoperation; (b) Microinstruction; (c) Micro- program; (d) Microcode.
The control memory in Fig. 7-2 has 4096 words of 24 bits each. a. How many bits are there in the control address register? b. How many bits are there in each of the four inputs shown going into the
Using the mapping procedure described in Fig. 7-3, give the first microinstruction address for the following operation code: (a) 0010; (b) 1011; (c) 1111.Fig. 7-3 Computer instruction: Mapping
Explain how the mapping from an instruction code to a microinstruction address can be done by means of a read-only memory. What is the advantage of this method compared to the one in Fig. 7-3?Fig.
Using Table 7-1, give the 9-bit microoperation field for the following microoperations: a. AC←AC + 1, DR←DR + 1 b. PC←PC + 1, DR←M[AR] c. DR←AC, AC←DRTable 7-1 TABLE 7-1 Symbols and
Why do we need the two multiplexers in the computer hardware configuration shown in Fig. 7-4? Is there another way that information from multiple sources can be transferred to a common
Add the following instructions to the computer of Sec 7-3 (EA is the effective address). Write the symbolic microprogram for each routine as in Table 7-2. (Note that AC must not change in value
Formulate a mapping procedure that provides eight consecutive microinstructions for each routine. The operation code has six bits and the control memory has 2048 words.
Using Table 7-1, convert the following symbolic microoperations to register transfer statements and to binary. a. READ, INCPC b. ACTDR, DRTAC c. ARTPC, DRTAC, WRITETable 7-1 TABLE 7-1 Symbols and
Suppose that we change the ADD routine listed in Table 7-2 to the following two microinstructions. ADD: READ I CALL INDR2 ADD U JMP
The following is a symbolic microprogram for an instruction in the computer defined in Sec. 7-3.a. Specify the operation performed when the instruction is executed. b. Convert the four
The computer of Sec. 7-3 has the following binary microprogram:a. Translate it to a symbolic microprogram as in Table 7-2. (FETCH is in address 64 and INDRCT in address 67.) b. List all the things
Write a symbolic microprogram routine for the ISZ (increment and skip if zero) instruction defined in Chap. 5 (Table 5-4). Use the microinstruction format of Sec. 7-3. Note that DR = 0 status
Write the symbolic microprogram routines for the BSA (branch and save address) instructions defined in Chap. 5 (Table 5-4). Use the microinstruction format of Sec. 7-3. Minimize the number of
Show how outputs 5 and 6 of decoder F3 in Fig. 7-7 are to be connected to the program counter PC.Fig. 7-7 FI PCTAR 3 x 8 decoder 7 6 5 4 3
A computer has 32-bit instructions and 12-bit addresses. If there are 250 two-address instructions, how many one-address instructions can be formulated?
Show how a 9-bit microoperation field in a microinstruction can be divided into subfields to specify 46 microoperations. How many microoperations can be specified in one microinstruction?
Assume that the input logic of the microprogram sequencer of Fig. 7-8 has four inputs, I2, I1, I0 T (test), and three outputs, S1, S0, and L. The operations that are performed in the unit are listed
Design a 7-bit combinational circuit incrementer for the microprogram sequencer of Fig. 7-8 (see Fig. 4-8). Modify the incrementer by including a control input D. When D= 0, the circuit increments by
A computer has 16 registers, an ALU (arithmetic logic unit) with 32 operations, and a shifter with eight operations, all connected to a common bus system. a. Formulate a control word for a
Insert an exclusive-OR gate between MUX 2 and the input logic of Fig. 7-8. One input to the gate comes from the test output of the multiplexer. The other input to the gate comes from a bit labeled P
A bus-organized CPU similar to Fig. 8-2 has 16 registers with 32 bits in each, an ALU, and a destination decoder. a. How many multiplexers are there in the A bus, and what is the size of each
The bus system of Fig. 8-2 has the following propagation delay times: 30 ns for the signals to propagate through the multiplexers, 80 ns to perform the ADD operation in the ALU, 20 ns delay in the
Specify the control word that must be applied to the processor of Fig. 8-2 to implement the following microoperations. a. R1←R2 + R3b. R4←R4 c. R5←R5 - 1 d. R6←inputFig. 8-2
Determine the microoperations that will be executed in the processor of Fig. 8-2 when the following 14-bit control words are applied. a. 00101001100101 b. 00000000000000 c. 01001001001100 d.
Let SP = 000000 in the stack of Fig. 8-3. How many items are there in the stack if: a. FULL = 1 and EMTY = 0?b. FULL = 0 and EMTY = 1?Fig. 8-3 FULL SP EMTY C B A DR Address 63 4 3 2 1 0
A stack is organized such that SP always points at the next empty location on the stack. This means that SP can be initialized to 4000 in Fig. 8-4 and the first item in the stack is stored in
Convert the following arithmetic expressions from infix to reverse Polish notation. a. A B + C D + E*F b. A B + A*(B*D + C*E) c. A + B* [CD+E * (F + G)] A [B+C (D + E)] F* (G + H) d.
Convert the following arithmetic expressions from reverse Polish notation to infix notation. a. A B C D E + * - / b. A B C D E * / - + c. A B C * / D - E F / + d. A B C D E F G + * + * + *
Convert the following numerical arithmetic expression into reverse Polish notation and show the stack operations for evaluating the numerical result. (3 + 4)[10(2 + 6) + 8]
Write a program to evaluate the arithmetic statement:a. Using a general register computer with three address instructions. b. Using a general register computer with two address instructions. c.
A first-in, first-out (FIFO) has a memory organization that stores information in such a manner that the item that is stored first is the first item that is retrieved. Show how a FIFO memory operates
The memory unit of a computer has 256K words of 32 bits each. The computer has an instruction format with four fields: an operation code field, a mode field to specify one of seven addressing modes,
A relative mode branch type of instruction is stored in memory at an address equivalent to decimal 750. The branch is made to an address equivalent to decimal 500. a. What should be the value of the
How many times does the control unit refer to memory when it fetches and executes an indirect addressing mode instruction if the instruction is (a) A computational type requiring an operand from
What must the address field of an indexed addressing mode instruction be to make it the same as a register indirect mode instruction?
An instruction is stored at location 300 with its address field at location 301. The address field has the value 400. A processor register R1 contains the number 200. Evaluate the effective address
An 8-bit register contains the value 01111011 and the carry bit is equal to 1. Perform the eight shift operations given by the instructions listed in Table 8-9. Each time, start from the initial
Assuming an 8-bit computer, show the multiple precision addition of the two 32-bit unsigned numbers listed below using the add with carry instruction. Each byte is expressed as a two-digit
What should be done in Fig. 11-14 to make the four VAD values equal to the binary equivalent of 76, 77, 78, and 79?Fig. 11-14
Perform the logic AND, OR, and XOR with the two binary strings 10011100 and 10101010.
Given the 16-bit value 1001101011001101. What operation must be performed in order to: a. Clear to 0 the first eight bits? b. Set to 1 the last eight bits? c. Complement the middle eight bits?
Represent the following signed numbers in binary using eight bits. +83; -83; +68; -68. a. Perform the addition (-83) + (+68) in binary and interpret the result obtained. b. Perform the subtraction
A two-word instruction is stored in memory at an address designated by the symbol W. The address field of the instruction (stored at W + 1) is designated by the symbol Y. The operand used during the
A computer uses RAM chips of 1024 x 1 capacity. a. How many chips are needed, and how should their address lines be connected to provide a memory capacity of 1024 bytes? b. How many chips are
An 8-bit computer has a 16-bit address bus. The first 15 lines of the address are used to select a bank of 32K bytes of memory. The high-order bit of the address is used to select a register which
A magnetic disk system has the following parameters: Ts = average time to position the magnetic head over a track R = rotation speed of disk in revolutions per second Nt = number of bits per
Show that the circuit labeled "check for zero output" in Fig. 8-8 is an 8-bit NOR gate.Fig. 8-8 V N S C C7 F₁ Check for zero output 8-bit ALU F₁-Fo 8 Output F B 8
Two signed numbers A and B represented in signed-2's complement form are compared by subtracting A - B. Status bits S, Z, and V are set or cleared depending on the result of the operation. (Note that
Two unsigned numbers A and B are compared by subtracting A - B. The carry status bit is considered as a borrow bit after a compare instruction in most commercial computers, so that C = 1 if A Table
An 8-bit computer has a register R. Determine the values of status bits C, S, Z, and V (Fig. 8-8) after each of the following instructions. The initial value of register R in each case is hexadecimal
It is necessary to design a digital circuit with four inputs C, S, Z, and V and 10 outputs, one for each of the branch conditions listed in Probs. 8-26 and 8-27. (The equal and unequal conditions are

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