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Questions and Answers of Electrical Engineering

For the network of Fig. 9.74:a. Determine the mathematical expression for the magnitude of the ratio Vo/Vi.b. Using the results of part (a), determine Vo/Vi at 100 Hz, 1 kHz, 2 kHz, 5 kHz, and 10
12. For the network of Fig. 9.74: a. Determine the mathematical expression for the angle by which Va leads V,. b. Determine the phase angle at ( = 100 Hz, 1 kHz, 2 kHz, 5 kHz, and 10 kHz, and plot
What frequency is one octave above 5 kHz? b. What frequency is one decade below 10 kHz? c. What frequency is two octaves below 20 kHz? d. What frequency is two decades above 1 kHz?
14. Repeat the analysis of Example 9.11 with ro = 40 kil. What is the effect on Avmid, (Ls, (Lc, (LE, and the resulting cutoff frequency?
15. For the network of Fig. 9.75:a. Determine re.b. Find Avmid = Vo/Vic. Calculate Zi.d- Find AvSmid = Vo/Vs.e. Determine (Ls,(Lc, and (LE.f. Determine the low cutoff frequency.g. Sketch the
Repeat Problem 15 for the emitter-stabilized network of Fig. 9.76.
Repeat Problem 15 for the emitter-follower network of Fig. 9.77.
Repeat Problem 15 for the common-base configuration of Fig. 9.78. Keep in mind that the common-base configuration is a noninverting network when you consider the Miller effect.
For the network of Fig. 9.79:a. Determine VGSQ and IDQ.b. Find gm0 and gm.c. Calculate the midband gain of Av = Vo/Vi.d. Determine Zi.e. Calculate Avs = Vo/Vs.f. Determine (LG, (Lc, and (Ls.g.
a. Determine the common logarithm of the number 2.2 × 103. b. Determine the natural logarithm of the number of part (a) using Eq. (9.4).
Repeat the analysis of Problem 19 with rd = 100 k(. Does it have an effect of any consequence on the results? If so, which elements?
Repeat the analysis of Problem 19 for the network of Fig. 9.80.What effect does the voltage-divider configuration have on the input impedance and the gain Avs compared to the biasing arrangement of
For the network of Fig. 9.75: a. Determine (Hi and (Ho. b. Find (( and (T. c. Sketch the frequency response for the high-frequency region using a Bode plot and determine the cutoff frequency.
Repeat the analysis of Problem 22 for the network of Fig. 9.76.
Repeat the analysis of Problem 22 for the network of Fig. 9.77.
Repeat the analysis of Problem 22 for the network of Fig. 9.78.
For the network of Fig. 9.79:a. Determine gm0 and gm.b. Find Av and Avs in the mid-frequency range.c. Determine (Hi and (Ho.d. Sketch the frequency response for the high-frequency region using a Bode
Repeat the analysis of Problem 26 for the network of Fig. 9.80.
The application of a 10-mV, 100-kHz square wave to an amplifier resulted in the output wave form of Fig. 9.81.a. Write the Fourier series expansion for the square wave through the ninth harmonic.b.
4. Calculate the power gain in decibels for each of the following cases. a. Po = 100W, Pi = 5 W. b. Po = 100mW, Pi = 5mW. c. Po = 100mW, Pi = 20 /(W.
6. Two voltage measurements made across the same resistance are V1 = 25 V and V2 = 100 V. Calculate the power gain in decibels of the second reading over the first reading.
5. Input and output voltage measurements of Vi = 10 mV and Vo = 25 V are made. What is the voltage gain in decibels?
a. The total decibel gain of a three-stage system is 120 dB. Determine the decibel gain of each stage if the second stage has twice the decibel gain of the first and the third has 2.7 times the
If the applied ac power to a system is 5 (W at 100 mV and the output power is 48 W, determine: a. The power gain in decibels. b. The voltage gain in decibels if the output impedance is 40 k(. c. The
Sketch the output waveform resulting in Fig. 10.69.
Calculate the output voltage, Vo, in the circuit of Fig. 10.73.
Calculate Vo in the circuit of Fig. 10.74.
Calculate the total offset voltage for the circuit of Fig. 10.75 for an op-amp with specified values of input offset voltage VI0 = 6 mV and input offset current I10 = 120 nA.
What is the range of the voltage-gain adjustment in the circuit of Fig. 10.63.
For an input of Vx = 50 mV in the circuit of Fig. 10.75, determine the maximum frequency that may be used. The op-amp slew rate SR = 0.4 V//xs.
Using the specifications listed in Table 10.3, calculate the typical offset voltage for the circuit connection of Fig. 10.75.
For the typical characteristics of the 741 op-amp, calculate the following values for the circuit of Fig. 10.75:a. ACL.b. Zic. Zo.
23. Calculate the CMRR (in dB) for the circuit measurements of Vd = 1 mV, Vo = 120mV, and Vc = 1 mV, Vo = 20 (V.
24. Determine the output voltage of an op-amp for input voltages of Vi = 200 (V and Vi2 = 140 (V. The amplifier has a differential gain of Ad = 6000 and the value of CMRR is: a. 200. b. 105.
What is the range of the output voltage in the circuit of Fig. 10.65 if the input can vary from 0.1 to 0.5 V?
What input must be applied to the input of Fig. 10.66 to result in an output of 2.4 V?
What range of output voltage is developed in the circuit of Fig. 10.67?
Calculate the output voltage developed by the circuit of Fig. 10.68 for R( = 330 k(.
Calculate the output voltage of the circuit in Fig. 10.68 for R( = 68 k(.
Show the connection (including pin information) of two LM358 stages connected as unity-gain amplifiers to provide the same output.
Calculate the lower and upper cutoff frequencies of the bandpass filter circuit in Fig. 11.59.
Calculate the output voltage in the circuit of Fig. 11.49.
Show the connection of an LM124 quad op-amp as a three-stage amplifier with gains of + 15, -22, and -30. Use a 420-kfl feedback resistor for all stages. What output voltage results for an input of V,
Show the connection of two op-amp stages using an LM358 IC to provide outputs that are 15 and -30 times larger than the input. Use a feedback resistor, RF = 150 k(, in all stages.
Calculate the output voltage for the circuit of Fig. 11.50 with inputs of V1 = 40 mV rms and V2 = 20 mV rms.
Determine the output voltage for the circuit of Fig. 11.51.
Determine the output voltage for the circuit of Fig. 11.52.
Show the connection (including pin information) of an LM124 IC stage connected as a unity-gain amplifier.
Calculate the input and output power for the circuit of Fig. 12.35. The input signal results in a base current of 5 mA rms.
Draw the circuit diagram of a class A transformer-coupled amplifier using an npn transistor.
Draw the circuit diagram of a class B npn push-pull power amplifier using transformer-coupled input.
For a class B amplifier providing a 22-V peak signal to an 8-( load and a power supply of VCC = 25 V, determine: a. Input power. b. Output power. c. Circuit efficiency.
For a class B amplifier with VCC = 25 V driving an 8-( load, determine: a. Maximum input power. b. Maximum output power. c. Maximum circuit efficiency.
Calculate the efficiency of a class B amplifier for a supply voltage of VCC = 22 V driving a 4-( load with peak output voltages of: a. VL(p) = 20 V. b. VL(p) =4V.
Sketch the circuit diagram of a quasi-complementary amplifier, showing voltage waveforms in the circuit.
For the class B power amplifier of Fig. 12.36, calculate:a. Maximum Po(ac).b. Maximum Pi(dc).c. Maximum %(.d. Maximum power dissipated by both transistors.
If the input voltage to the power amplifier of Fig. 12.36 is 8-V rms, calculate:a. Pi(dc).b. Po(ac).c. %(.d. Power dissipated by both power output transistors.
For the power amplifier of Fig. 12.37, calculate:a. Po(ac).b. Pi(dc).c. %(.d. Power dissipated by both output transistors.
Calculate the harmonic distortion components for an output signal having fundamental amplitude of 2.1 V, second harmonic amplitude of 0.3 V, third harmonic component of 0.1 V, and fourth harmonic
Calculate the input power dissipated by the circuit of Fig. 12.35 if RB is changed to 1.5 k(.
Calculate the total harmonic distortion for the amplitude components of Problem 19.
Calculate the second harmonic distortion for an output waveform having measured values of VCEmin = 2.4 V, VCEQ = 10 V, and VCEmax = 20 V.
For distortion readings of D2 = 0.15, D3 = 0.01, and D4 = 0.05, with /1 = 3.3 A and RC = 4 (, calculate the total harmonic distortion fundamental power component and total power.
Determine the maximum dissipation allowed for a 100-W silicon transistor (rated at 25°C) for a derating factor of 0.6 W/°C at a case temperature of 150°C.
A160-Wsiliconpowertransistoroperatedwithaheatsink ((SA, = 1.5°C/W) has(JC = 0.5°C/W and a mounting insulation of (CS = 0.8°C/W. What maximum power can be handled by the transistor at an ambient
What maximum output power can be delivered by the circuit of Fig. 12.35 if RB is changed to 1.5 k(?
If the circuit of Fig. 12.35 is biased at its center voltage and center collector operating point, what is the input power for a maximum output power of 1.5 W?
A transformer-coupled class A amplifier drives a 16-( speaker through a 3.87:1 transformer. Using a power supply of VCC = 36 V, the circuit delivers 2 W to the load. Calculate: a. P(ac) across
Calculate the efficiency of the circuit of Problem 8 if the bias current is ICQ = 150 mA.
Draw the diagram of a 741 op-amp operated from ±15-V supplies with Vi(-) = 0 V and Vi( + ) = +5 V. Include terminal pin connections.
What is the maximum count interval using a 12-stage counter operated at a clock rate of 20 MHz?
Sketch the circuit of a 555 timer connected as an astable multivibrator for operation at 350 kHz. Determine the value of capacitor C needed using RA = RB = 7.5 k(.
Draw the circuit of a one-shot using a 555 timer to provide one time period of 20 (s. If RA = 7.5 k(, what value of C is needed?
Sketch the input and output waveforms for a one-shot using a 555 timer triggered by a 10-kHz clock for RA = 5.1 k( and C = 5 nF.
Calculate the center frequency of a VCO using a 566 IC as in Fig. 13.22 for R1 = 4.7 kfl, R2 = 1.8 k(, R3 = 11 k(, and C1 = 0.001 (F,
What frequency range results in the circuit of Fig. 13.23 for C1 = 0.001 (F?
Determine the capacitor needed in the circuit of Fig. 13.22 to obtain a 200-kHz output.
Sketch the output waveform for the circuit of Fig. 13.40.
What is the lock range of the PLL circuit in Fig. 13.26b for R1 = 4.7 k( and C1 = 0.001 (F?
Draw a circuit diagram of a 311 op-amp showing an input of 10 V rms applied to the inverting input and the plus input to ground. Identify all pin numbers.
Draw the resulting output waveform for the circuit of Fig. 13.41.
Draw the circuit diagram of a zero-crossing detector using a 339 comparator stage with ±12-V supplies.
Sketch the output waveform for the circuit of Fig. 13.42.
Describe the operation of the circuit in Fig. 13.43.
Sketch a five-stage ladder network using 15-k( and 30-k( resistors.
For the transistor Colpitts oscillator of Fig. 14.27 and the following circuit values, calculate the oscillation frequency: L = 100 (H, LRFC = 0.5 mH, C, = 0.005 (F, C2 = 0.01 (F, and CC = 10(F.
Calculate the oscillator frequency for an FET Hartley oscillator as in Fig. 14.29 for the following circuit values: C = 250pF, L1 = 1.5mH, L2 = 1.5 mH, and M = 0.5 mH.
Calculate the oscillation frequency for the transistor Hartley circuit of Fig. 14.30 and the following circuit values: LRFC = 0.5 mH, L1 = 750(H, L2 = 750(H, M = 150(H, and C = 150 pF.
Design a unijunction oscillator circuit for operation at (a) 1 kHz and (b) 150 kHz.
Calculate the gain, input, and output impedances of a voltage-series feedback amplifier having A = -300, Ri = 1.5k(, Ro = 50k(, and ( = -1/15.
Calculate the gain with and without feedback for an FET amplifier as in Fig. 14.7 for circuit values R1, = 800k(, R2 = 200k(, Ro = 40k(, RD = 8k(, and gm = 5000 (S.
For a circuit as in Fig. 14.11 and the following circuit values, calculate the circuit gain and the input and output impedances with and without feedback: RB = 600k(, RE = l.2k(, RC = 4.7 k(, and ( =
Calculate the operating frequency of a BJT phase-shift oscillator as in Fig. 14.21b for R = 6k(, C= 1500 pF, and RC = 18 k(.
For an FET Colpitts oscillator as in Fig. 14.26 and the following circuit values determine the circuit oscillation frequency: C1 = 750 pF, C2 = 2500 pF, and L = 40 (H.
A 500-(F capacitor provides a load current of 200 mA at 8% ripple. Calculate the peak rectified voltage obtained from the 60-Hz supply and the dc voltage across the filter capacitor.
Calculate the percentage ripple for the voltage developed across a 120-(F filter capacitor when providing a load current of 80 mA. The full-wave rectifier operating from the 60-Hz supply develops a
An RC filter stage (R = 33 (, C = 120 (F) is used to filter a signal of 24 V dc with 2 V rms operating from a full-wave rectifier. Calculate the percentage ripple at the output of the RC section for
A simple capacitor filter has an input of 40 V dc. If this voltage is fed through an RC filter section (R = 50(, C = 40 (F), what is the load current for a load resistance of 500(?
Calculate the rms ripple voltage at the output of an RC filter section that feeds a 1 -k( load when the filter input is 50 V dc with 2.5-V rms ripple from a full-wave rectifier and capacitor filter.
If the no-load output voltage for Problem 17 is 50 V, calculate the percentage voltage regulation with a 1-k( load.

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