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Computer Organization and Design The Hardware Software Interface 5th edition David A. Patterson, John L. Hennessy - Solutions

Calculate by hand 8.625 × 101 divided by -4.875 × 100. Show all the steps necessary to achieve your answer. Assume there is a guard, a round bit, and a sticky bit, and use them if necessary. Write the final answer in both the 16-bit floating point format described in Exercise 3.27 and in decimal
Calculate the product of –8.0546875 × 100 and -1.79931640625 × 10–1 by hand, assuming A and B are stored in the 16-bit half precision format described in Exercise 3.27. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps; however, as is done in the
Calculate the sum of 2.6125 × 101 and 4.150390625 × 10-1 by hand, assuming A and B are stored in the 16-bit half precision described in Exercise 3.27. Assume 1 guard, 1 round bit, and 1 sticky bit, and round to the nearest even. Show all the steps.Exercise 3.27IEEE 754-2008 contains a half
The Hewlett-Packard 2114, 2115, and 2116 used a format with the left most 16 bits being the fraction stored in two’s complement format, followed by another 16-bit fi eld which had the left most 8 bits as an extension of the fraction (making the fraction 24 bits long), and the rightmost 8 bits
IEEE 754-2008 contains a half precision that is only 16 bits wide. The left most bit is still the sign bit, the exponent is 5 bits wide and has a bias of 15, and the mantissa is 10 bits long. A hidden 1 is assumed. Write down the bit pattern to represent -1.5625 × 10-1 assuming a version of this
Write down the binary bit pattern to represent -1.5625 × 10-1 assuming a format similar to that employed by the DEC PDP-8 (the left most 12 bits are the exponent stored as a two’s complement number, and the rightmost 24 bits are the fraction stored as a two’s complement number). No hidden 1 is
Write down the binary representation of the decimal number 63.25 assuming it was stored using the single precision IBM format (base 16, instead of base 2, with 7 bits of exponent).
Write down the binary representation of the decimal number 63.25 assuming the IEEE 754 double precision format.
Write down the binary representation of the decimal number 63.25 assuming the IEEE 754 single precision format.
What decimal number does the bit pattern 0×0C000000 represent if it is a floating point number? Use the IEEE 754 standard.
Using a table similar to that shown in Figure 3.10, calculate 74 divided by 21 using the hardware described in Figure 3.11. You should show the contents of each register on each step. Assume A and B are unsigned 6-bit integers. Th is algorithm requires a slightly different approach than that shown
Using a table similar to that shown in Figure 3.10, calculate 74 divided by 21 using the hardware described in Figure 3.8. You should show the contents of each register on each step. Assume both inputs are unsigned 6-bit integers.Figure 3.8Figure 3.10 Divisor Shift right 64 bits Quotient 64-bit ALU
As discussed in the text, one possible performance enhancement is to do a shift and add instead of an actual multiplication. Since 9 × 6, for example, can be written (2 × 2 × 2 + 1) × 6, we can calculate 9 × 6 by shifting 6 to the left 3 times and then adding 6 to that result. Show the best
Calculate the time necessary to perform a multiply using the approach given in Figure 3.7 if an integer is 8 bits wide and an adder takes 4 time units.Figure 3.7 Mplier31 • Mcand Mplier30 • Mcand Mplier29 • Mcand Mplier28 • Mcand Mplier3 • Mcand Mplier2 • Mcand Mplier1 • Mcand Mpliero
Calculate the time necessary to perform a multiply using the approach described in the text (31 adders stacked vertically) if an integer is 8 bits wide and an adder takes 4 time units.
Calculate the time necessary to perform a multiply using the approach given in Figures 3.3 and 3.4 if an integer is 8 bits wide and each step of the operation takes 4 time units. Assume that in step 1a an addition is always performed€”either the multiplicand will be added, or a zero will
Using a table similar to that shown in Figure 3.6, calculate the product of the hexadecimal unsigned 8-bit integers 62 and 12 using the hardware described in Figure 3.5. You should show the contents of each register on each step.Figure 3.5Figure 3.6 Multiplicand 32 bits 32-bit ALU Shift right
Using a table similar to that shown in Figure 3.6, calculate the product of the octal unsigned 6-bit integers 62 and 12 using the hardware described in Figure 3.3. You should show the contents of each register on each step.Figure 3.3Figure 3.6 Multiplicand Shift left 64 bits Multiplier Shift right
Assume 151 and 214 are signed 8-bit decimal integers stored in two’s complement format. Calculate 151 + 214 using saturating arithmetic. The result should be written in decimal. Show your work.
Assume 185 and 122 are signed 8-bit decimal integers stored in sign-magnitude format. Calculate 185 - 122. Is there overflow, underflow, or neither?
Assume 185 and 122 are signed 8-bit decimal integers stored in sign-magnitude format. Calculate 185 + 122. Is there overflow, underflow, or neither?
Assume 185 and 122 are unsigned 8-bit decimal integers. Calculate 185 – 122. Is there overflow, underflow, or neither?
What is 4365 - 3412 when these values represent signed 12-bit octal numbers stored in sign-magnitude format? The result should be written in octal. Show your work.
Convert 5ED4 into a binary number. What makes base 16 (hexadecimal) an attractive numbering system for representing values in computers?
Assume for a given processor the CPI of arithmetic instructions is 1, the CPI of load/store instructions is 10, and the CPI of branch instructions is 3. Assume a program has the following instruction breakdowns: 500 million arithmetic instructions, 300 million load/store instructions, 100 million
Using your code from Exercise 2.43 as an example, explain what happens when two processors begin to execute this critical section at the same time, assuming that each processor executes exactly one instruction per cycle.Exercise 2.43Write the MIPS assembly code to implement the following C
If the current value of the PC is 0x1FFFf000, can you use a single branch instruction to get to the PC address as shown in Exercise 2.39?Exercise 2.39Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100two and stores that value to register $t1.
If the current value of the PC is 0x00000600, can you use a single branch instruction to get to the PC address as shown in Exercise 2.39?Exercise 2.39Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100two and stores that value to register $t1.
If the current value of the PC is 0x00000000, can you use a single jump instruction to get to the PC address as shown in Exercise 2.39?Exercise 2.39Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100two and stores that value to register $t1.
Write the MIPS assembly code that creates the 32-bit constant 0010 0000 0000 0001 0100 1001 0010 0100two and stores that value to register $t1.
Consider the following code:Assume that the register $t1 contains the address 0x1000 0000 and the register $t2 contains the address 0x1000 0010. Note the MIPS architecture utilizes big-endian addressing. Assume that the data (in hexadecimal) at address 0x1000 0000 is: 0x11223344. What value is
Right before your function f from Exercise 2.34 returns, what do we know about contents of registers $t5, $s3, $ra, and $sp? Keep in mind that we know what the entire function f looks like, but for function func we only know its declaration.Exercise 2.34Translate function f into MIPS assembly
Can we use the tail-call optimization in this function? If no, explain why not. If yes, what is the difference in the number of executed instructions in f with and without the optimization?
Functions can oft en be implemented by compilers “in-line.” An in-line function is when the body of the function is copied into the program space, allowing the overhead of the function call to be eliminated. Implement an “in-line” version of the C code above in MIPS assembly. What is the
Implement the following C code in MIPS assembly. What is the total number of MIPS instructions needed to execute the function int fib(int n){ if (n==0) return 0; else if (n 1) == return 1; else return fib( n-1) + fib(n-2);
Translate the following loop into C. Assume that the C-level integer i is held in register $t1, $s2 holds the C-level integer called result, and $s0 holds the base address of the integer MemArray. addi $t1, $0, $0 $s1, 0($s0) LOOP: 1w add $s2, $s2, $s1 addi $s0, $s0, 4 addi $t1, $t1, 1 slti $t2,
How many MIPS instructions does it take to implement the C code from Exercise 2.27? If the variables a and b are initialized to 10 and 1 and all elements of D are initially 0, what is the total number of MIPS instructions that is executed to complete the loop?Exercise 2.27Translate the following C
Consider the following MIPS loop:1. Assume that the register $t1 is initialized to the value 10. What is the value in register $s2 assuming $s2 is initially zero?2. For each of the loops above, write the equivalent C code routine. Assume that the registers $s1, $s2, $t1, and $t2 are integers A, B,
The following instruction is not included in the MIPS instruction set:rpt $t2, loop # if(R[rs]>0) R[rs]=R[rs]−1, PC=PC+4+BranchAddr1. If this instruction were to be implemented in the MIPS instruction set, what is the most appropriate instruction format?2. What is the shortest sequence of MIPS
Assume the following register contents:$t0 = 0xAAAAAAAA, $t1 = 0x123456781. [5] <§2.6> For the register values shown above, what is the value of $t2 for the following sequence of instructions?2. For the register values shown above, what is the value of $t2 for the following sequence of
Suppose the program counter (PC) is set to 0x2000 0000. Is it possible to use the jump (j) MIPS assembly instruction to set the PC to the address as 0x4000 0000? Is it possible to use the branch-on-equal (beq) MIPS assembly instruction to set the PC to this same address?
Assume $t0 holds the value 0x00101000. What is the value of $t2 aft er the following instructions? $t2, $0, slt $t0 bne $t2, $0, ELSE DONE ELSE: addi $t2, $t2, 2 DONE:
For the following C statement, write a minimal sequence of MIPS assembly instructions that does the identical operation. Assume $t1 = A, $t2 = B, and $s1 is the base address of C.A = C[0] << 4;
Provide a minimal set of MIPS instructions that may be used to implement the following pseudoinstruction:not $t1, $t2 // bit-wise invert
Find the shortest sequence of MIPS instructions that extracts bits 16 down to 11 from register $t0 and uses the value of this field to replace bits 31 down to 26 in register $t1 without changing the other 26 bits of register $t1.
Assume that we would like to expand the MIPS register file to 128 registers and expand the instruction set to contain four times as many instructions.1. How this would this affect the size of each of the bit fields in the R-type instructions?2. How this would this affect the size of each of the bit
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields:op = 0 x 23, rs = 1, rt = 2, const = 0 x 4
Provide the type, assembly language instruction, and binary representation of instruction described by the following MIPS fields:op = 0, rs = 3, rt = 2, rd = 3, shamt = 0, funct = 34
Provide the type and hexadecimal representation of following instruction: sw $t1, 32($t2)
Provide the type and assembly language instruction for the following binary value: 0000 0010 0001 0000 1000 0000 0010 0000two.
Assume that $s0 holds the value 128ten.1. For the instruction add $t0, $s0, $s1, what is the range(s) of values for $s1 that would result in overflow?2. For the instruction sub $t0, $s0, $s1, what is the range(s) of values for $s1 that would result in overflow?3. For the instruction sub $t0, $s1,
Assume that registers $s0 and $s1 hold the values 0x80000000 and 0xD0000000, respectively.1. What is the value of $t0 for the following assembly code? add $t0, $s0, $s12. Is the result in $t0 the desired result, or has there been overflow?3. For the contents of registers $s0 and $s1 as specified
Translate the following MIPS code to C. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. addi $t0, $s6, 4 add $t1, $s6, $0 $t1, 0($t0) $t0,
For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program. Use a minimal number of MIPS assembly instructions.f = g + (h − 5);
For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. $t0, $s0,
For the following MIPS assembly instructions above, what is a corresponding C statement?add f, g, hadd f, i, f
Th e table below shows 32-bit values of an array stored in memory.Address .............Data24 ..........................238 ..........................432 ..........................336 ..........................640 ..........................11. For the memory locations in the table above, write C
For the MIPS assembly instructions in Exercise 2.4, rewrite the assembly code to minimize the number if MIPS instructions (if possible) needed to carry out the same function.Exercise 2.4For the MIPS assembly instructions below, what is the corresponding C statement? Assume that the variables f, g,
For the following C statement, what is the corresponding MIPS assembly code? Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively.B[8] = A[i−j];
Aside from the smart cell phones used by a billion people, list and describe four other types of computers.
Another pitfall cited in Section 1.10 is expecting to improve the overall performance of a computer by improving only one aspect of the computer. Consider a computer running a program that requires 250 s, with 70 s spent executing FP instructions, 85 s executed L/S instructions, and 40 s spent
Th e eight great ideas in computer architecture are similar to ideas from other fields. Match the eight ideas from computer architecture, “Design for Moore’s Law”, “Use Abstraction to Simplify Design”, “Make the Common Case Fast”, “Performance via Parallelism”, “Performance via
Describe the steps that transform a program written in a high-level language such as C into a representation that is directly executed by a computer processor.
Assume a color display using 8 bits for each of the primary colors (red, green, blue) per pixel and a frame size of 1280 × 1024.a. What is the minimum size in bytes of the frame buff er to store a frame?b. How long would it take, at a minimum, for the frame to be sent over a 100 Mbit/s network?
Consider three diff erent processors P1, P2, and P3 executing the same instruction set. P1 has a 3 GHz clock rate and a CPI of 1.5. P2 has a 2.5 GHz clock rate and a CPI of 1.0. P3 has a 4.0 GHz clock rate and has a CPI of 2.2.a. Which processor has the highest performance expressed in instructions
Consider two different implementations of the same instruction set architecture. Th e instructions can be divided into four classes according to their CPI (class A, B, C, and D). P1 with a clock rate of 2.5 GHz and CP Is of 1, 2, 3, and 3, and P2 with a clock rate of 3 GHz and CP Is of 2, 2, 2, and
Compilers can have a profound impact on the performance of an application. Assume that for a program, compiler A results in a dynamic instruction count of 1.0E9 and has an execution time of 1.1 s, while compiler B results in a dynamic instruction count of 1.2E9 and an execution time of 1.5 s.a.
Th e Pentium 4 Prescott processor, released in 2004, had a clock rate of 3.6 GHz and voltage of 1.25 V. Assume that, on average, it consumed 10 W of static power and 90 W of dynamic power.The Core i5 Ivy Bridge, released in 2012, had a clock rate of 3.4 GHz and voltage of 0.9 V. Assume that, on
Assume for arithmetic, load/store, and branch instructions, a processor has CP Is of 1, 12, and 5, respectively. Also assume that on a single processor a program requires the execution of 2.56E9 arithmetic instructions, 1.28E9 load/store instructions, and 256 million branch instructions. Assume
Assume a 15 cm diameter wafer has a cost of 12, contains 84 dies, and has 0.020 defects/cm2. Assume a 20 cm diameter wafer has a cost of 15, contains 100 dies, and has 0.031 defects/cm2.1. Find the yield for both wafers.2. Find the cost per die for both wafers.3. If the number of dies per wafer is
The results of the SPEC CPU 2006 bzip2 benchmark running on an AMD Barcelona has an instruction count of 2.389E12, an execution time of 750 s, and a reference time of 9650 s.1. Find the CPI if the clock cycle time is 0.333 ns.2. Find the SPEC ratio.3. Find the increase in CPU time if the number of
Section 1.10 cites as a pitfall the utilization of a subset of the performance equation as a performance metric. To illustrate this, consider the following two processors. P1 has a clock rate of 4 GHz, average CPI of 0.9, and requires the execution of 5.0E9 instructions. P2 has a clock rate of 3
Assume a program requires the execution of 50 × 106 FP instructions, 110 × 106 INT instructions, 80 × 106 L/S instructions, and 16 × 106 branch instructions. The CPI for each type of instruction is 1, 1, 4, and 2, respectively.Assume that the processor has a 2 GHz clock rate.1. By how much must

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