New Semester Started Get 50% OFF Study Help! --h --m --s Claim Now

Question Answers

Textbooks

Find textbooks, questions and answers

Oops, something went wrong!

Change your search query and then try again

Result Not Found

Books FREE
Study Help
Tutors
AI Study Planner NEW
Sell Books

Search
Sign In
Register

study help
computer science
computer organization design

Computer Organization And Design The Hardware Software Interface 4th Revised Edition David A. Patterson, John L. Hennessy - Solutions

For problems below, use the information about access time for every type of memory in the following table.Find how long it takes to read a file from a lash memory if it takes 2 microseconds from the cache memory. a. b. Cache 5 ns 7 ns DRAM 50 ns 70 ns Flash Memory 5 με 15 μs Magnetic Disk 5
The table below shows the number of instructions per processor core on a multi core processor as well as the average CPI for executing the program on 1, 2, 4, or 8 cores. Using this data, you will be exploring the speedup of applications on multicore processors.If using a single core, find the
For problems below, use the information in the following table.Find the number of instructions for P2 that reduces its execution time to that of P3. a. b. Processor P1 P2 P3 P1 P2 P3 Clock Rate 3 GHz 2.5 GHz 4 GHz 2 GHz 3 GHz 4 GHz No.
The following table shows the number of instructions for a program.If the number of load instructions can be reduced by one half, what is the speedup and the CPI? a. b. Arith 650 750 Store 100 250 Load 600 500 Branch 50 500 Total 1400 2000
The following table shows data for further benchmarks.Find the change in the SPECratio for the change described in 1.12.5. a. b. Name libquantum astar CPI 1.61 1.79 Clock Rate 4 GHz 4 GHz SPECratio 19.8 9.1
The table below shows instruction-type breakdown for different programs. Using this data, you will be exploring the performance trade-offs for different changes made to an MIPS processor.Assuming that computes take 1 cycle, loads and store instructions take 2 cycles, and branches take 3 cycles,
The following table shows data for further benchmarks.Determine the clock rate if the CPI is reduced by 15% and the CPU time by 20% while the number of instructions is unchanged. a. b. Name libquantum astar Execution Time (seconds) 960 690 CPI 1.61 1.79 Clock Rate 3 GHz 3 GHz
Consider two different implementations, P1 and P2, of the same instruction set. There are five classes of instructions (A, B, C, D, and E) in the instruction set. P1 has a clock rate of 4 GHz, and P2 has a clock rate of 6 GHz. The average number of cycles for each instruction class for P1 and P2
Another common performance Figure is MFLOPS (million of floating-point operations per second), defined as MFLOPS = No. FP operations / (execution time × 106) but this figure has the same problems as MIPS. Consider the program in the following table, running on the two processors below.Find the
Consider the following values for voltage in each generation.Find the geometric mean of the voltage ratios in the generations since the Pentium. Processor 80286 (1982) 80386 (1985) 80486 (1989) Pentium (1993) Pentium Pro (1997) Pentium 4 Willamette (2001) Pentium 4 Prescott (2004) Core 2 Ketsfield
The following table shows the instruction type breakdown per processor of given applications executed in different numbers of processors.Assume that each processor has a 2 GHz clock rate.How much is the execution time of the program improved if the CPI of INT and FP instructions is reduced by 40%
Suppose that the industry trends show that a new process generation varies as follows.Assuming a Core 2 processor with a clock rate of 2.667 GHz, a power consumption of 95 W, and a voltage of 1.1 V, find the voltage and clock rate of this processor for the next process generation.
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Part of a computer called central processor unit 1. 2. 3. 4. virtual worlds desktop
Consider now the dynamic power dissipation of different versions of a given processor for three different voltages given in the following table.Determine the geometric mean of the power variations between versions. a. b. 1.2 V 75 W 62 W 1.0 V 60 W 50 W 0.8 V 35 W 30 W
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Thousands of processors forming a large cluster 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Microprocessors containing several processors in the same chip 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Desktop computer without a screen or keyboard usually accessed via a network 1. 2. 3. 4. virtual
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.A computer used to running one predetermined application or collection of software 1. 2. 3. 4. virtual
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Special language used to describe hardware components 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.computer delivering good performance to single users at low cost 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Program that translates statements in high-level language to assembly language 1. 2. 3. 4. virtual
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Program that translates symbolic instructions to binaryinstructions 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.High-level language for business data processing 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Binary language that the processor can understand 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Commands that the processors understand 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.High-level language for scientiic computation 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Symbolic representation of machine instructions 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Interface between user’s program and hardware providing a variety of services and supervision
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Software/programs developed by the users 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Binary digit (value 0 or 1) 1. 2. 3. 4. virtual worlds desktop computers 11. 12. 13. servers low-end
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.High-level language used to write application and system software 1. 2. 3. 4. virtual worlds desktop
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Software layer between the application software and the hardware that includes the operating system and
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.Portable language composed of words and algebraic expressions that must be translated into assembly
Find the word or phrase from the list below that best matches the description in the following questions. Use the numbers to the left of words in the answer. Each answer should be used only once.1012 or 240 bytes 1. 2. 3. 4. virtual worlds desktop computers 11. 12. 13. servers low-end
In the following problems, the data table contains various modifications that could be made to the MIPS instruction set architecture. You will investigate the impact of these changes on the instruction format of the MIPS architecture.If the instruction set of the MIPS processor is modified, the
The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is satisfied. Note that x86 instructions refer to 8 bits as a byte, 16 bits as a word, and 32 bits as a double word. The first three problems in this Exercise
This exercise explores ASCII and Unicode conversion. The following table shows strings of characters.Translate the strings into hexadecimal ASCII byte values. a. hello world b. 0123456789
In the following problems, we will be investigating memory operations in the context of an MIPS processor. The table below shows the values of an array stored in memory. Assume the base address of the array is stored in register $s6 and offset it with respect to the base address of the array.For
In this exercise, you will be asked to write an MIPS assembly program that converts strings into the number format as speciied in the table.Write a program in MIPS assembly language to convert an ASCII number string with the conditions listed in the table above, to an integer. Your program should
The following problems deal with translating from C to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of
Assume that the data (in hexadecimal) at address 0x1000 0000 is:What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0xFFFF FFFF.Assume that the register $t1 contains the address 0x1000 0000 and the register $t2 contains
Assume the following instruction breakdown given for executing a given program:What is the execution time for the processor if the operation frequency is 5 GHz?The CPI of the different instruction types is given in the following table. Arithmetic Load/Store Branch Instructions (in
The problems in this Exercise refer to the following function, given as array code:Translate this function into MIPS assembly. a. void copy(int a[], int b[], int n) { int i; for(i=0; i-n;i++) a[i]=b[i]; b. } void shift(int a[], int n) { int i; for(i=0; i-n-1; i++) a[i]=a[i+1]; }
The following problems explore number conversions from signed and unsigned binary numbers to decimal numbers.For the patterns above, what base 10 number does the binary number represent, assuming that it is a two’s complement integer? a. 0010 0100 1001 0010 0100 1001 0010 0100 two b. 0101 1111
In the following problems, the data table contains the values for registers $t0 and $t1. You will be asked to perform several MIPS logical operations on these registers.For the lines above, what is the value of $t2 for the following sequence of instructions?sll $t2, $t0, 44or $t2, $t2, $t1 $t0 b.
The MIPS architecture requires word-sized accesses (lw and sw) to be word-aligned, i.e., the lowermost 2 bits of the address must both be zero. If an address is not word-aligned, the processor raises a “bus error” exception. Explain how this alignment requirement affects the execution of this
In this exercise, you will explore 32-bit constants in MIPS. For the following problems, you will be using the binary data in the table below.Write the MIPS assembly code that creates the 32-bit constants listed above and stores that value to register $t1. a. b. 0010 0000 0000 0001 0100 1001 0010
The following figure shows the placement of a bit field in register $t0.In the following problems, you will be asked to write MIPS instructions to extract the bits “Field” from register $t0 and place them into register $t1 at the location indicated in the following table.Find the shortest
The table below contains ARM assembly code. In the following problems, you will translate ARM assembly code to MIPS.For the table above, translate this ARM assembly code to MIPS assembly code. Assume that ARM registers r0, r1, and r2 hold the same values as MIPS registers $s0, $s1, and $s2,
For this exercise, you will explore the range of branch and jump instructions in MIPS. For the following problems, use the hexadecimal data in the table below.If the PC is at address 0x00000000, how many branch (no jump instructions) do you need to get to the address in the table above? a.
For these problems, the table holds some logical operations that are not included in the MIPS instruction set. How can these instructions be implemented?The logical instructions above are not included in the MIPS instruction set, but are described above. If the value of $t2 = 0x00FFA5A5 and the
The ARM processor has a few different addressing modes that are not supported in MIPS. The following problems explore these new addressing modes.Identify the type of addressing mode of the ARM assembly instructions in the table above. a. b. LDR r0. [rl. #4] LDMIA r0!, [rl-r3] ; r0 = ; rl ;
In the following problems, you will be exploring different addressing modes in the MIPS instruction set architecture. These different addressing modes are listed in the table below.In the table above are different addressing modes of the MIPS instruction set. Give an example MIPS instructions that
The following problems deal with sign extension and over low. Registers $s0 and $s1 hold the values as shown in the table below. You will be asked to perform an MIPS assembly language instruction on these registers and show the result.For the contents of registers $s0 and $s1 as specified above,
For these problems, the table holds various binary values for register $t0. Given the value of $t0, you will be asked to evaluate the outcome of different branches.Suppose that register $t0 contains a value from above and $t1 has the valueNote the result of executing these instructions on
The following table contains MIPS assembly code for a lock. Refer to the definition of the ll and sc pairs of MIPS instructions.For each test and fail of the store conditional, how many instructions need to be executed? a. try: MOV LL ADDI SC BEQZ MOV R3, R4 R2,0 (R2) R2, R2, 1 R3,0 (R1) R3,try R4,
For these problems, there are several instructions that are not included in the MIPS instruction set are shown.The table above contains some instructions not included in the MIPS instruction set and the description of each instruction. Why are these instructions not included in the MIPS instruction
The first three problems in this Exercise refer to a critical section of the formlock(lk);operationunlock(lk);where the “operation” updates the shared variable shvar using the local (nonshared) variable x as follows:Write the MIPS assembly code for this critical section, assuming that the
The ARM processor has an interesting way of supporting immediate constants. This exercise investigates those differences. The following table contains ARM instructions.Write the equivalent MIPS code for the ARM assembly code above. a. b. ADD, r3, r2, rl, LSR #4 ADD, r3, r2. r2 :r3 = r2 + (rl >>
This exercise explores the differences between the MIP and x86 instruction sets. The following table contains x86 assembly code.Write pseudo code for the given routine. c b. START: mov eax, 3 push eax mov eax, 4 mov ecx, 4 add eax. ecx pop ecx add eax, ecx START: mov ecx, 100 mov eax, 0 LOOP: add
For these problems, the table holds some C code. You will be asked to evaluate these C code statements in MIPS assembly code.For the table above, draw a control-low graph of the C code. a. b. for(i=0; i
The table below contains the link-level details of two different procedures. In this exercise, you will be taking the place of the linker.Link the object files above to form the executable file header. Assume that Procedure A has a text size of 0x140 and data size of 0x40 and Procedure B has a text
The following problems explore translating from C to MIPS. Assume that the variables f, g, h, and i are given and could be considered 32-bit integers as declared in a C program.For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly
Assembler instructions are not a part of the MIPS instruction set, but often appear in MIPS programs. The table below contains some MIPS assembly instructions that get translated to actual MIPS instructions.For each assembly instruction in the table above, produce a minimal sequence of actual MIPS
The table below contains various values for register $s1. You will be asked to evaluate if there would be overflow for a given operation.Assume that register $s0 = 0x70000000 and $s1 has the value as given in the table. If the instruction: add $s0, $s0, $s1 is executed, will there be overflow?
For the following problems, the table holds C code functions. Assume that the first function listed in the table is called first. You will be asked to translate these C code routines into MIPS assembly.Implement the C code in the table in MIPS assembly. What is the total number of MIPS instructions
The following problems deal with translating from C to MIPS. Assume that the variables g, h, i, and j are given and could be considered 32-bit integers as declared in a C program.For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly
This exercise deals with recursive procedure calls. For the following problems, the table has an assembly code fragment that computes the factorial of a number. However, the entries in the table have errors, and you will be asked to ix these errors. For number n, factorial of n = 1 x 2 x 3 x .. ..
In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to interpret the bits as MIPS instructions into assembly code and determine what format of MIPS instruction the bits represent.For the binary entries above, what instruction do
The following problems explore translating from C to MIPS. Assume that the variables f and g are given and could be considered 32-bit integers as declared in a C program.For the C statements above, what is the corresponding MIPS assembly code? Use a minimal number of MIPS assembly instructions. a.
The first three problems in this exercise assume that the function swap, is defined in C as follows:Translate this function into MIPS assembler code. a. b. void swap(int *p, int *q) { int temp; temp=*p; *p=*q: *q-temp: } void swap(int *p. int *q) { *p=*p+*q: *q*p-*q; *p=*p-*q;
Assume that the stack and the static data segments are empty and that the stack and global pointers start at address 0x7fff fffc and 0x1000 8000, respectively. Assume the calling conventions as speciied in Figure 2.11 and that function inputs are passed using registers $a0–$a3 and returned in $b. int my_global 100; main() { } int { int x = 10; 20: } int y int z; z } int { } int my_global = 100; main$
In the following problems, the data table contains bits that represent the opcode of an instruction. You will be asked to translate the entries into assembly code and determine what format of MIPS instruction the bits represent.What binary number does the above hexadecimal number represent? a.
The following problems deal with translating from C to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and$s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively.For the C statements above, what
In the following problems, the data table contains various modifications that could be made to the MIPS instruction set architecture. You will investigate the impact of these changes on the instruction format of the MIPS architecture.If the instruction set of the MIPS processor is modified, the
This exercise explores ASCII and Unicode conversion. The following table shows strings of characters.Translate the strings into 16-bit Unicode (using hex notation and the Basic Latin character set). a. hello world b. 0123456789
The x86 instruction set includes the REP prefix that causes the instruction to be repeated a given number of times or until a condition is satisfied. Note that x86 instructions refer to 8 bits as a byte, 16 bits as a word, and 32 bits as a double word. The first three problems in this Exercise
In the following problems, we will be investigating memory operations in the context of an MIPS processor. The table below shows the values of an array stored in memory. Assume the base address of the array is stored in register $s6 and offset it with respect to the base address of the array.For
The first three problems in this exercise assume that the function swap, is defined in C as follows:What needs to change in the sort function? a. b. void swap(int *p, int *q) { int temp; temp=*p; *p=*q: *q-temp: } void swap(int *p. int *q) { *p=*p+*q: *q*p-*q; *p=*p-*q;
The following problems deal with translating from C to MIPS. Assume that the variables f, g, h, i, and j are assigned to registers $s0, $s1, $s2, $s3, and $s4, respectively. Assume that the base address of the arrays A and B are in registers $s6 and $s7, respectively. Assume that the elements of
Suppose that new, more powerful arithmetic instructions are added to the instruction set. On average, through the use of these more powerful arithmetic instructions, we can reduce the number of arithmetic instructions needed to execute a program by 25%, and the cost of increasing the clock cycle
The problems in this Exercise refer to the following function, given as array code:Convert this function into pointer-based code (in C). a. void copy(int a[], int b[], int n) { int i; for(i=0; i-n;i++) a[i]=b[i]; b. } void shift(int a[], int n) { int i; for(i=0; i-n-1; i++) a[i]=a[i+1]; }
In the following problems, the data table contains the values for registers $t0 and $t1. You will be asked to perform several MIPS logical operations on these registers.For the values in the table above, what is the value of $t2 for the following sequence of instructions?sll $t2, $t0, 4andi $t2,
In this exercise, you will explore 32-bit constants in MIPS. For the following problems, you will be using the binary data in the table below.If the current value of the PC is 0x00000000, can you use a single jump instruction to get to the PC address as shown in the table above? a. b. 0010 0000
The following problems explore number conversions from signed and unsigned binary numbers to decimal numbers.For the patterns above, what base 10 number does the binary number represent, assuming that it is an unsigned integer? a. 0010 0100 1001 0010 0100 1001 0010 0100 two b. 0101 1111 1011 1110
The table below contains ARM assembly code. In the following problems, you will translate ARM assembly code to MIPS.For the ARM assembly instructions in the table above, show the bit fields that represent the ARM instructions. a. b. ADD ADC r0, r1, r2 r0, rl, r2 CMP r0, #4 ADDNE rl, rl,
The following figure shows the placement of a bit field in register $t0.In the following problems, you will be asked to write MIPS instructions to extract the bits “Field” from register $t0 and place them into register $t1 at the location indicated in the following table.Find the shortest
The first three problems in this Exercise refer to the following function, given in MIPS assembly. Unfortunately, the programmer of this function has fallen prey to the pitfall of assuming that MIPS is a word-addressed machine, but in fact MIPS is byte-addressed.Note that in MIPS assembly the
For this exercise, you will explore the range of branch and jump instructions in MIPS. For the following problems, use the hexadecimal data in the table below.If the PC is at address 0x00000000, how many jump instructions (no jump register instructions or branch instructions) are required to get to
For these problems, the table holds some logical operations that are not included in the MIPS instruction set. How can these instructions be implemented?The logical instructions above are not included in the MIPS instruction set, but can be synthesized using one or more MIPS assembly instructions.
The ARM processor has a few different addressing modes that are not supported in MIPS. The following problems explore these new addressing modes.For the ARM assembly instructions above, write a sequence of MIPS assembly instructions to accomplish the same data transfer. a. b. LDR r0. [rl. #4] LDMIA
In the following problems, you will be exploring different addressing modes in the MIPS instruction set architecture. These different addressing modes are listed in the table below.For the instructions in 2.27.1, what is the instruction format type used for the given instruction? a. Base or
The following problems deal with sign extension and over low. Registers $s0 and $s1 hold the values as shown in the table below. You will be asked to perform an MIPS assembly language instruction on these registers and show the result.For the contents of registers $s0 and $s1 as specified above,
For these problems, the table holds various binary values for register $t0. Given the value of $t0, you will be asked to evaluate the outcome of different branches.Suppose that register $t0 contains a value from the table above and is compared against the value X, as used in the MIPS instruction
Assume that the data (in hexadecimal) at address 0x1000 0000 is:What value is stored at the address pointed to by register $t2? Assume that the memory location pointed to $t2 is initialized to 0x0000 0000.Assume that the register $t1 contains the address 0x1000 0000 and the register $t2 contains
The following table contains MIPS assembly code for a lock. Refer to the definition of the ll and sc pairs of MIPS instructions.For the load locked/store conditional code above, explain why this code may fail. a. try: MOV LL ADDI SC BEQZ MOV R3, R4 R2,0 (R2) R2, R2, 1 R3,0 (R1) R3,try R4, R2
For these problems, there are several instructions that are not included in the MIPS instruction set are shown.The table above contains some instructions not included in the MIPS instruction set and the description of each instruction. If these instructions were to be implemented in the MIPS
The first three problems in this Exercise refer to a critical section of the formlock(lk);operationunlock(lk);where the “operation” updates the shared variable shvar using the local (nonshared) variable x as follows:Repeat problem 2.29.1, but this time use ll/sc to perform an atomic update of
The ARM processor has an interesting way of supporting immediate constants. This exercise investigates those differences. The following table contains ARM instructions.If the register R1 had the constant value of 8, rewrite your MIPS code to minimize the number of MIPS assembly instructions needed.
This exercise explores the differences between the MIP and x86 instruction sets. The following table contains x86 assembly code.For the code in the table above, what is the equivalent MIPS for the given routine? c b. START: mov eax, 3 push eax mov eax, 4 mov ecx, 4 add eax. ecx pop ecx add eax,

Showing 700 - 800 of 1073

1
2
3
4
5
6
7
8
9
10
11

Step by Step Answers

Services

Sitemap
Fun
Definitions
Become Tutor
Used Textbooks
Study Help Categories
Recent Questions
Expert Questions
Campus Wear
Sell Your Books

Company Info

Security
Copyrights
Privacy Policy
Terms & Conditions
SolutionInn Fee
Scholarship
Online Quiz
Give Feedback, Get Rewards

Get In Touch

About Us
Contact Us
Career
Jobs
FAQ
Student Discount
Campus Ambassador

Secure Payment

Download Our App

© 2026 SolutionInn. All Rights Reserved