Digital Design and Computer Architecture 2nd edition David Harris, Sarah Harris - Solutions

Write an HDL module for the circuit in Exercise 3.31. Data from problem 3.31Analyze the FSM shown in Figure 3.72. Write the state transition and output tables and sketch the state transition diagram. Describe in words what the FSM does. X- CLK CLK
Write an HDL module for the circuit in Exercise 3.32. Data from problem 3.32Repeat Exercise 3.31 for the FSM shown in Figure 3.73. Recall that the s and r register inputs indicate set and reset, respectively. Data From Problem 31Analyze the FSM shown in Figure 3.72. Write the state
Write an HDL module for the circuit in Exercise 3.33 Data from problem 3.33Ben Bitdiddle has designed the circuit in Figure 3.74 to compute a registered four-input XOR function. Each two-input XOR gate has a propagation delay of 100 ps and a contamination delay of 55 ps. Each flip-flop has a
Write an HDL module for the circuit in Exercise 3.34. You may use the full adder from Section 4.2.5. Data from problem 3.34You are designing an adder for the blindingly fast 2-bit RePentium Processor. The adder is built from two full adders such that the carry out of the first adder is the
What does it mean for a signal to be declared tri in SystemVerilog?
Rewrite the syncbad module from HDL Example 4.29. Use nonblocking assignments, but change the code to produce a correct synchronizer with two flip-flops.
Consider the following two System Verilog modules. Do they have the same function? Sketch the hardware each one implies. module codel(input logic clk, a, b, c. output logic y): logic x: always_ff @(posedge clk) begin x (= a & b; y
Repeat Exercise 4.48 if the <= is replaced by = in every assignment. Data from problem 48Consider the following two SystemVerilog modules. Do they have the same function? Sketch the hardware each one implies. module codel(input logic clk, a, b, c. output logic y): logic x: always_ff
The following SystemVerilog modules show errors that the authors have seen students make in the laboratory. Explain the error in each module and show how to fix it. (a) (b)(c)(d)(e)(f)(g)(h)(i)(j) module latch(input logic clk. input logic [3:0] d. output reg [3:0] q): always @(clk) if
In VHDL, why is it necessary to write q < = '1' when state = S0 else '0' ;rather than simply q < = (state =S0);
Each of the following VHDL modules contains an error. For brevity, only the architecture is shown; assume that the library use clause and entity declaration are correct. Explain the error and show how to fix it. (a) (b)(c)(d)(e)(f)(g) architecture synth of latch is begin process(clk)
What is the largest possible result of multiplying two unsigned N-bit numbers?
Design two adders: a 64-bit ripple-carry adder and a 64-bit carry look ahead adder with 4-bit blocks. Use only two-input gates. Each two-input gate is 15 μm 2 , has a 50 ps delay, and has 20 fF of total gate capacitance. You may assume that the static power is negligible. (a) Compare the
Binary coded decimal (BCD) representation uses four bits to encode each decimal digit. For example, 4210is represented as 01000010BCD· Explain in words why processors might use BCD representation.
Explain why a designer might choose to use a ripple-carry adder instead of a carry-look ahead adder.
Design hardware to add two 8-bit unsigned BCD numbers. Sketch a schematic for your design, and write an HDL module for the BCD adder. The inputs are A, B, and Cin, and the outputs are S and Cout. Cin and Cout are 1-bit carries and A, B, and S are 8-bit BCD numbers.
The prefix network shown in Figure 5.7 uses black cells to compute all of the prefixes. Some of the block propagate signals are not actually necessary. Design a “gray cell” that receives G and P signals for bits i:k and k−1:j but produces only Gi:j, not Pi:j. Redraw the prefix network,
The prefix network shown in Figure 5.7 is not the only way to calculate all of the prefixes in logarithmic time. The Kogge-Stone network is another common prefix network that performs the same function using a different connection of black cells. Research Kogge-Stone adders and draw a schematic
Recall that an N-input priority encoder has log2N outputs that encodes which of the N inputs gets priority.(a) Design an N-input priority encoder that has delay that increases logarithmically with N. Sketch your design and give the delay of the circuit in terms of the delay of its circuit
Design the following comparators for 32-bit numbers. Sketch the schematics.(a) Not equal(b) Greater than(c) Less than or equal to
Design the 32-bit ALU shown in Figure 5.15 using your favorite HDL. You can make the top-level module either behavioral or structural. A N. F2 *N BB Cout [N-1] S YN F1.0 to Zero extend
Add an Overflow output to the 32-bit ALU from Exercise 5.9. The output is TRUE when the result of the adder overflows. Otherwise, it is FALSE.(a) Write a Boolean equation for the Overflow output.(b) Sketch the Overflow circuit.(c) Design the modified ALU in an HDL.
Add a Zero output to the 32-bit ALU from Exercise 5.9. The output is TRUE when Y == 0.
Write a testbench to test the 32-bit ALU from Exercise 5.9, 5.10, or 5.11. Then use it to test the ALU. Include any test vector files necessary. Be sure to test enough corner cases to convince a reasonable skeptic that the ALU functions correctly.
Design a shifter that always shifts a 32-bit input left by 2 bits. The input and output are both 32 bits. Explain the design in words and sketch a schematic. Implement your design in your favorite HDL.
Design 4-bit left and right rotators. Sketch a schematic of your design. Implement your design in your favorite HDL.
Design an 8-bit left shifter using only 24 2:1 multiplexers. The shifter accepts an 8-bit input A and a 3-bit shift amount, shamt2:0. It produces an 8-bit output Y. Sketch the schematic.
Explain how to build any N-bit shifter or rotator using only N log2N 2:1 multiplexers.
The funnel shifter in Figure 5.64 can perform any N-bit shift or rotate operation. It shifts a 2N-bit input right by k bits. The output Y is the N least significant bits of the result. The most significant N bits of the input are called B and the least significant N bits are called C. By choosing
Find the critical path for the 4 × 4 multiplier from Figure 5.18 in terms of an AND gate delay (tAND) and an adder delay (tFA) What is the delay of an N × N multiplier built in the same way?
Design a multiplier that handles two’s complement numbers.
A sign extension unit extends a two’s complement number from M to N (N > M) bits by copying the most significant bit of the input into the upper bits of the output. It receives an M-bit input A and produces an N-bit output Y. Sketch a circuit for a sign extension unit with a 4-bit input and an
A zero extension unit extends an unsigned number from M to N bits (N > M) by putting zeros in the upper bits of the output. Sketch a circuit for a zero extension unit with a 4-bit input and an 8-bit output. Write the HDL for your design.
Repeat Exercise 5.31 for the following two’s complement binary fixed-point numbers.(a) 011101.10101(b) 100110.11010(c) 101000.00100Data from problem 31Convert the following two’s complement binary fixed-point numbers to base 10. The implied binary point is explicitly shown to aid in your
Compute 111001.0002/001100.0002 in binary using the standard division algorithm from elementary school. Show your work.
Express the following base 10 numbers in 16-bit fixed-point sign/ magnitude format with eight integer bits and eight fraction bits. Express your answer in hexadecimal. (a) −13.5625(b) 42.3125(c) −17.15625
What is the range of numbers that can be represented by the following number systems?(a) 24-bit unsigned fixed-point numbers with 12 integer bits and 12 fraction bits(b) 24-bit sign and magnitude fixed-point numbers with 12 integer bits and 12 fraction bits(c) 24-bit two’s complement fixed-point
Convert the following two’s complement binary fixed-point numbers to base 10. The implied binary point is explicitly shown to aid in your interpretation.(a) 0101.1000(b) 1111.1111(c) 1000.0000
Express the following base 10 numbers in 12-bit fixed-point sign/ magnitude format with six integer bits and six fraction bits. Express your answer in hexadecimal.(a) −30.5(b) 16.25(c) −8.078125
Express the base 10 numbers in Exercise 5.25 in 16-bit fixed-point two’s complement format with eight integer bits and eight fraction bits. Express your answer in hexadecimal. Data from Problem 25(a) −13.5625(b) 42.3125(c) −17.15625
Express the base 10 numbers in Exercise 5.26 in 12-bit fixed-point two’s complement format with six integer bits and six fraction bits. Express your answer in hexadecimal. Data from Problem 26(a) −30.5(b) 16.25(c) −8.078125
Express the base 10 numbers in Exercise 5.25 in IEEE 754 single precision floating-point format. Express your answer in hexadecimal. Data from Problem 25(a) −13.5625(b) 42.3125(c) −17.15625
Express the base 10 numbers in Exercise 5.26 in IEEE 754 single precision floating-point format. Express your answer in hexadecimal. Data from Problem 26(a) −30.5(b) 16.25(c) −8.078125
Add the following IEEE 754 single-precision floating-point numbers.(a) C0123456 + 81C564B7(b) D0B10301 + D1B43203(c) 5EF10324 + 5E039020
Add the following IEEE 754 single-precision floating-point numbers.(a) C0D20004 + 72407020(b) C0D20004 + 40DC0004(c) (5FBE4000 + 3FF80000) + DFDE4000 (Why is the result counter intuitive? Explain.)
Expand the steps in for performing floating-point addition to work for negative as well as positive floating-point numbers. Expand the steps in section 5.3.2 for performing floating-point addition to work for negative as well as positive floating-point numbers.
Consider IEEE 754 single-precision floating-point numbers.(a) How many numbers can be represented by IEEE 754 single-precision floatingpoint format? You need not count ±∞ or NaN. 286 CHAPTER FIVE Digital Building Blocks(b) How many additional numbers could be represented if ±∞ and NaN were
Consider the following decimal numbers: 245 and 0.0625.(a) Write the two numbers using single-precision floating-point notation. Give your answers in hexadecimal.(b) Perform a magnitude comparison of the two 32-bit numbers from part (a). In other words, interpret the two 32-bit numbers as two’s
An incrementer adds 1 to an N-bit number. Build an 8-bit incrementer using half adders.
Design a single-precision floating-point adder using your favorite HDL. Before coding the design in an HDL, sketch a schematic of your design. Simulate and test your adder to prove to a skeptic that it functions correctly. You may consider positive numbers only and use round toward zero (truncate).
In this problem, you will explore the design of a 32-bit floating-point multiplier. The multiplier has two 32-bit floating-point inputs and produces a 32-bit floating-point output. You may consider positive numbers only and use round toward zero (truncate). You may also ignore the special cases
In this problem, you will explore the design of a 32-bit prefix adder.(a) Sketch a schematic of your design.(b) Design the 32-bit prefix adder in an HDL. Simulate and test your adder to prove that it functions correctly.(c) What is the delay of your 32-bit prefix adder from part (a)? Assume that
Ben Bitdiddle has invented a circuit with the transfer characteristics shown in Figure 1.47 that he would like to use as a buffer. Will it work? Why or why not? He would like to advertise that it is compatible with LVCMOS and LVTTL logic. Can Ben’s buffer correctly receive inputs from those logic
Is it possible to assign logic levels so that a device with the transfer characteristics shown in Figure 1.46 would serve as a buffer? If so, what are the input and output low and high levels (VIL,VOL,VIH, and VOH) and noise margins (NML and NMH)? If not, explain why not. Vout 5- 4 - 3- 2- 1 Vin 0
Repeat Exercise 1.78 for the transfer characteristics shown in Figure 1.45. Voue 2 - Vn т 4 3. 4. 3.
Is it possible to assign logic levels so that a device with the transfer characteristics shown in Figure 1.44 would serve as an inverter? If so, what are the input and output low and high levels (VIL, VOL, VIH, and VOH) and noise margins (NML and NMH)? If not, explain why not. Vout Vn 4
How many different truth tables exist for Boolean functions of N variables?
There are 16 different truth tables for Boolean functions of two variables. List each truth table. Give each one a short descriptive name (such as OR, NAND, and so on).
A three-input OR-AND-INVERT (OAI) gate shown in Figure 1.43 produces a FALSE output if C is TRUE and A or B is TRUE. Otherwise, it produces a TRUE output. Complete a truth table for the gate. в -Y c-
A three-input AND-OR (AO) gate shown in Figure 1.42 produces a TRUE output if both A and B are TRUE, or if C is TRUE. Complete a truth table for the gate. A- в- C- -Y Figure 1.42 Three-input AND-OR gate
A majority gate produces a TRUE output if and only if more than half of its inputs are TRUE. Complete a truth table for the three-input majority gate shown in Figure 1.41. 8-MAJ-Y Figure 1.41 Three-input majority gate
Draw the symbol, Boolean equation, and truth table for (a) A four-input OR gate (b) A three-input XNOR gate (c) A five-input NAND gate
Draw the symbol, Boolean equation, and truth table for(a) A three-input OR gate (b) A three-input exclusive OR (XOR) gate (c) A four-input XNOR gate
Repeat Exercise 1.69 but convert from an arbitrary base b1 to another base b2, as specified by the user. Support bases up to 16, using the letters of the alphabet for digits greater than 9. The user should enter b1, b2, and then the number to convert in base b1. The program should print the
Write a program in your favorite language (e.g., C, Java, Perl) to convert numbers from binary to decimal. The user should type in an unsigned binary number. The program should print the decimal equivalent.
Ben Bitdiddle and Alyssa P. Hacker are having an argument. Ben says, “All integers greater than zero and exactly divisible by six have exactly two 1’s in their binary representation.” Alyssa disagrees. She says, “No, but all such numbers have an even number of 1’s in their
Answer the following questions related to BCD systems.(a) Write 37110 in BCD(b) Convert 000110000111BCD to decimal(c) Convert 10010101BCD to binary(d) Explain the disadvantages of BCD when compared to binary representations of numbers
In a binary coded decimal (BCD) system, 4 bits are used to represent a decimal digit from 0 to 9. For example, 3710 is written as 00110111BCD.(a) Write 28910 in BCD(b) Convert 100101010001BCD to decimal(c) Convert 01101001BCD to binary(d) Explain why BCD might be a useful way to represent numbers
Draw a number line analogous to Figure 1.11 for 3-bit biased numbers with a bias of 3. 6 -8 -7 -6 -5 -4 13 14 15 -3 -2 -1 3 4 10 11 12 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Unsigned 1000 1001 1010 1011 1100 1101 1110 1111 o000 0001 0010 0011 0100 0101 0110
Convert the following decimal numbers to 6-bit two’s complement binary numbers and subtract them. Indicate whether or not the difference overflows a 6-bit result.(a) 1810 − 1210 (b) 3010 − 910 (c) −2810 − 310 (d) −1610 −2110
Convert the following decimal numbers to 5-bit two’s complement binary numbers and subtract them. Indicate whether or not the difference overflows a 5-bit result.(a) 910 − 710 (b) 1210 − 1510 (c) −610 − 1110 (d) 410 − 810
Perform the following additions of unsigned hexadecimal numbers. Indicate whether or not the sum overflows an 8-bit (two hex digit) result. (a) 716 + 916 (b) 1316 + 2816 (c) AB16 + 3E16 (d) 8F16 + AD16
Perform the following additions of unsigned hexadecimal numbers. Indicate whether or not the sum overflows an 8-bit (two hex digit) result. (a) 716 + 916 (b) 1316 + 2816 (c) AB16 + 3E16 (d) 8F16 + AD16
Convert the following decimal numbers to 6-bit two’s complement binary numbers and add them. Indicate whether or not the sum overflows a 6-bit result. (a) 1610 + 910 (b) 2710 + 3110 (c) −410 + 1910 (d) 310 + −3210 (e) −1610 + −910 (f) −2710 + −3110
Repeat Exercise 1.53, assuming that the binary numbers are in two’s complement form.Data From problem 53(a) 100110012 + 010001002 (b) 110100102 + 101101102
Repeat Exercise 1.52, assuming that the binary numbers are in two’s complement form.Data From Problem 52(a) 10012 + 01002 (b) 11012 + 10112
Perform the following additions of unsigned binary numbers. Indicate whether or not the sum overflows an 8-bit result.(a) 100110012 + 010001002 (b) 110100102 + 101101102
Perform the following additions of unsigned binary numbers. Indicate whether or not the sum overflows a 4-bit result.(a) 10012 + 01002 (b) 11012 + 10112
Draw a number line analogous to Figure 1.11 for 2-bit unsigned, two’s complement, and sign/magnitude numbers. -8 -7 -6 -5 -4 -3 -2 -1 1 3 6 7 8 9. 10 11 12 13 14 15 Unsigned 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1000 1001 1010 1011 1100 1101 1110 1111
Draw a number line analogous to Figure 1.11 for 3-bit unsigned, two’s complement, and sign/magnitude numbers. -8 -7 -6 -5 -4 -3 -2 -1 1 3 6 7 8 9. 10 11 12 13 14 15 Unsigned 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1000 1001 1010 1011 1100 1101 1110 1111
A memory on the Pentium II microprocessor is organized as a rectangular array of bits with 28 rows and 29 columns. Estimate how many bits it has without using a calculator.
Estimate the value of 231 without using a calculator.
Hard disk manufacturers use the term “megabyte” to mean 106 bytes and “gigabyte” to mean 109 bytes. How many real GBs of music can you store on a 50 GB hard disk?
USB 3.0 can send data at 5 Gbits/sec. How many bytes can it send in 1 minute?
A particular DSL modem operates at 768 kbits/sec. How many bytes can it receive in 1 minute?
How many bytes are in a 32-bit word? How many nibbles are in the word?
How many 7-bit two’s complement numbers are greater than 0? How many are less than 0? How would your answers differ for sign/magnitude numbers?
How many 5-bit two’s complement numbers are greater than 0? How many are less than 0? How would your answers differ for sign/magnitude numbers?
Convert each of the following octal numbers to binary, hexadecimal, and decimal.(a) 238 (b) 458 (c) 3718 (d) 25608
Convert each of the following octal numbers to binary, hexadecimal, and decimal.(a) 428 (b) 638 (c) 2558 (d) 30478
Base 8 is referred to as octal. Convert each of the numbers from Exercise 1.26 to octal.Data From Problem 26(a) 1410 (b) 5210 (c) 33910 (d) 71110
Base 8 is referred to as octal. Convert each of the numbers from Exercise 1.25 to octal.Data from Problem 25(a) 4210 (b) 6310 (c) 22910 (d) 84510
Repeat Exercise 1.34 if the numbers are unsigned rather than two’s complement.Data From Problem 34(a) 01112 (b) 10012
Repeat Exercise 1.33 if the numbers are unsigned rather than two’s complement.Data from Problem 33(a) 01012 (b) 10102
Convert the following 4-bit two’s complement numbers to 8-bit two’s complement numbers.(a) 01112 (b) 10012
Convert the following 4-bit two’s complement numbers to 8-bit two’s complement numbers.(a) 01012 (b) 10102
Repeat Exercise 1.30, but convert to 8-bit sign/magnitude numbers.Data From Problem 30(a) 2410 (b) −5910 (c) 12810 (d) −15010 (e) 12710
Repeat Exercise 1.29, but convert to 8-bit sign/magnitude numbers.Data From Problem 29(a) 4210 (b) −6310 (c) 12410 (d) −12810 (e) 13310
Convert the following decimal numbers to 8-bit two’s complement numbers or indicate that the decimal number would overflow the range.(a) 2410 (b) −5910 (c) 12810 (d) −15010 (e) 12710
Convert the following decimal numbers to 8-bit two’s complement numbers or indicate that the decimal number would overflow the range.(a) 4210 (b) −6310 (c) 12410 (d) −12810 (e) 13310

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Digital Design and Computer Architecture 2nd edition David Harris, Sarah Harris - Solutions

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