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computer science
digital systems principles and application
Digital Systems Principles And Application 12th Edition Ronald Tocci, Neal Widmer, Gregory Moss - Solutions
What is the central hardware feature of a DSP?
Which ADC is best included in microcontroller-based data acquisition systems?
Name three types of ADCs that do not use a DAC.
Why are voltage DACs generally slower than current DACs?
What will happen to both resolution and full-scale output when VREF is increased by 20 percent?
Answer the following concerning the ADC0804.(a) What is its resolution in bits?(b) What is the normal analog input voltage range?(c) Describe the functions of the C̅S̅, W̅R̅, and R̅D̅ inputs.(d) What is the function of the I̅N̅T̅R̅ output?(e) Why does it have two separate grounds?(f) What
What is the minimum sample frequency needed to reconstruct an analog signal?
What is the percentage resolution of an eight-bit DAC?
Why does conversion time increase with the value of the analog input voltage?
What does a computer often do with the data that it receives from an ADC?
(a) What is the resolution (step size) of the DAC of Example 11-2? Describe the staircase signal out of this DAC.(b) For the DAC of Example 11-2, determine VOUT for a digital input of 10001.Data from Example 11-2A five-bit D/A converter produces VOUT = 0.2 V for a digital input of 00001. Find the
What is the function of the EOC signal?
What advantage does a DSP filter have over an analog filter circuit?
List some applications of pipelined ADCs.
List three limitations of the AD7524.
Cite two advantages and one disadvantage of the dual-slope ADC.
State the major advantage and disadvantage of a flash converter.
Describe offset error and its effect on a DAC output.
What will the resolution be if the value of RF in Figure 11-5 is changed to 800Ω?Figure 11-5 De C B 1 ΚΩ MSB 2 ΚΩ 4 ΚΩ ww 8 ΚΩ LSB Digital inputs: O V or 5 V (a) RF = 1 k Op- amp +Vs -Vs VOUT D 0000 0 oooo 0 0 0 1 1 1 1 1 1 1 1 Input
True or false: The conversion time for a SAC increases as the analog voltage increases.
What is the weight of the MSB of the DAC of question 1?Data from Question 1An eight-bit DAC has an output of 3.92 mA for an input of 01100010. What are the DAC’s resolution and full-scale output?
Explain quantization error.
What is the function of an ADC?
A five-bit D/A converter produces VOUT = 0.2 V for a digital input of 00001. Find the value of VOUT for an input of 11111.
Where is the approximate digital equivalent of VA when the conversion is complete?
What is the typical source of digital data for a DSP to process?
True or false: The amplifiers in an S/H circuit are used to provide voltage amplification.
List an application of dual-slop integrating A/D converters.
What is the role of the WR line on the AD7524?
What is the main element of a voltage-to-frequency ADC?
How many comparators would a 12-bit flash converter require? How many resistors?
What is settling time?
A certain six-bit DAC uses binary-weighted resistors. If the MSB resistor is 20 kΩ, what is the LSB resistor?
What is its principal disadvantage compared with the digital-ramp converter?
What is digitizing a signal?
An eight-bit DAC has an output of 3.92 mA for an input of 01100010. What are the DAC’s resolution and full-scale output?
Describe the basic operation of the digital-ramp ADC.
What is the function of a transducer?
What is the function of the comparator in the ADC?
List three common failure modes associated with DACs.
List three applications of DACs.
List 3 applications of analog interfacing.
What is a major application of DSP?
What is the advantage of this multiplexing scheme?
Describe the function of a S/H circuit.
Can the AD7524 be connected to a tristate bus?
List applications of sigma/delta A/D converters.
What do multiple subranging stages produce in a pipelined ADC?
True or false: A flash ADC does not contain a DAC.
Define full-scale error.
What is the advantage of R/2R ladder DACs over those that use binary-weighted resistors?
How many states are in the half-step sequence?
What are the inputs for the wave-drive mode?
How many degrees of rotation result from one compete cycle through the full-step sequence in Table 10-1?Table 10-1 Full-Step Sequence Coil 3210 1010 1001 0101 0110 Half-Step Wave-Drive Sequence Sequence Coil 3210 Coil 3210 1010 1000 1001 0001 0101 0100 0110 0010 1000 0001 0100 0010
Assume that the BCD counter in Figure 10-47 consists of three cascaded BCD stages and their associated displays. If the unknown frequency is between 1 kpps and 9.99 kpps, which range (sample interval) should be selected using the MUX of Figure 10-49 ?Figure 10-47Figure 10-49 Clock System generator
What are the inputs for the direct-drive mode?
At what stage should you decide how to measure success?
If a frequency of 3792 pps is applied to the input of the frequency counter, what will the counter read under each of the following sample intervals?(a) 1 second (b) 0.1 second (c) 10 ms
What are the four modes of operation for this stepper motor driver?
Name the steps of project management.
Assume that a frequency counter uses a four-digit BCD counter. Determine the maximum frequency that can be measured using each of the following sample intervals:(a) 1 second (b) 0.1 second (c) 0.01 second
Consider a digital thermostat in which the measured room temperature is converted to a digital number and applied to the A inputs of a comparator. The desired room temperature, entered from a keypad, is stored in a register that is connected to the B inputs. If A < B, the furnace should be
Describe the operation of the eight-bit comparison arrangement in Figure 9-40(b) for the following cases:(a) A7A6A5A4A3A2A1A0 = 10101111; B7B6B5B4B3B2B1B0 = 10110001(b) A7A6A5A4A3A2A1A0 = 10101111; B7B6B5B4B3B2B1B0 = 10101001Figure 9-40(b) +5 V Low-order bits A3 A₂ A₁ Ao B3 B₂ B₁ Bo A>B IAB
How are certain inputs (e.g., lamp test) given precedence over other inputs (e.g., RBI) in the HDL code in this section?
The security monitoring system can be developed as a project.(a) Write a project definition with specifications for this system.(b) Define three major blocks of this project.(c) Identify the signals that interconnect the blocks.(d) At what frequency must the oscillator run for a 2.5-Hz flash
If you wanted to latch data from the keypad into a 74174 register, which signal from the keypad would you connect to the clock of the register? Draw the circuit.
A technician tests the circuit of Figure 9-4 as described in Example 9-7, and she obtains the following results: all of the outputs work except O̅16 to O̅19 and O̅24 to O̅27, which are permanently HIGH. What is the most probable circuit fault?Data from Example 9-7A technician tests the circuit
Rewrite the code of the four-bit comparator of Figures 9-69 or 9-70 to make an eight-bit comparator without using macrofunctions.Figure 9-69Figure 9-70 LEMAFETO GONNA 1 2 3 4 5 6 7 8 9 10 11 12 SUBDESIGN fig9_69 ( a[3..0], b[3..01 agtb, altb, aeqb > BEGIN IF : INPUT; : OUTPUT; al]> b[]
(a) Expand the circuit of Figure 9-24 to display the contents of two three-stage BCD counters.(b) Count the number of connections in this circuit, and compare it with the number required if a separate decoder/driver and display were used for each stage of each counter.Figure 9-24
How many full steps must occur for a complete revolution?
How many degrees of rotation result from one complete cycle through the half-step sequence in Table 10-1?Table 10-1 Full-Step Sequence Coil 3210 1010 1001 0101 0110 Half-Step Wave-Drive Sequence Sequence Coil 3210 Coil 3210 1010 1000 1001 0001 0101 0100 0110 0010 1000 0001 0100 0010
(a) What is the expression relating the output and inputs of a DAC?(b) Define step size of a DAC.(c) Define resolution of a DAC.(d) Define full scale.(e) Define percentage resolution.(f) True or false: A 10-bit DAC will have a smaller resolution than a 12-bit DAC for the same full-scale output.(g)
An eight-bit DAC produces an output voltage of 2.0 V for an input code of 01100100. What will the value of VOUT be for an input code of 10110011?
Determine the weight of each input bit for the DAC of Problem 11-2.Data from Problem 11-2An eight-bit DAC produces an output voltage of 2.0 V for an input code of 01100100. What will the value of VOUT be for an input code of 10110011?
What is the resolution of the DAC of Problem 11-2? Express it in volts and as a percentage.Data from Problem 11-2An eight-bit DAC produces an output voltage of 2.0 V for an input code of 01100100. What will the value of VOUT be for an input code of 10110011?
What is the resolution in volts of a 10-bit DAC whose F.S. output is 5 V?
How many bits are required for a DAC so that its F.S. output is 10 mA and its resolution is less than 40 μA?
What is the percentage resolution of the DAC of Figure 11-34? What is the step size if the top step is 2 V?Figure 11-34 1 kHz CLOCK Three-bit ripple counter D/A converter VOUT OV Spikes 1 2 V
What is the cause of the negative-going spikes on the VOUT waveform of Figure 11-34?Figure 11-34 1 kHz CLOCK Three-bit ripple counter D/A converter VOUT OV Spikes 1 2 V
Assuming a 12-bit DAC with perfect accuracy, how close to 250 rpm can the motor speed be adjusted in Figure 11-4?Figure 11-4 日 Computer DAC lOUT 0-2 mA Current amp. Motor 0—1000 rpm
A 12-bit DAC has a full-scale output of 15.0 V. Determine the step size, the percentage resolution, and the value of VOUT for an input code of 011010010101.
A microcontroller has an eight-bit output port that is to be used to drive a DAC. The DAC that is available has 10 input bits and has a full-scale output of 10 V. The application requires a voltage that ranges between 0 and 10 V in steps of 50 mV or smaller. Which eight bits of the 10-bit DAC will
The step size of the DAC of Figure 11-5 can be changed by changing the value of RF. Determine the required value of RF for a step size of 0.5 V. Will the new value of RF change the percentage resolution?Figure 11-5 D C B 1 ΚΩ MSB 2 ΚΩ 4 ΚΩ 8 ΚΩ LSB Digital inputs: O V or 5 V (a) R = 1
Assume that the output of the DAC in Figure 11-7(a) is connected to the op-amp of Figure 11-7(b).(a) With VREF = 5 V, R = 20 kΩ, and RF = 10 k, determine the step size and the full-scale voltage at VOUT.(b) Change the value of RF so that the full-scale voltage at VOUT is –2 V.(c) Use this new
You need a DAC that can span 12 V with a resolution of 20 mV or less. How many bits are needed?
What is the advantage of the DAC of Figure 11-8 over that of Figure 11-7, especially for a larger number of input bits?Figure 11-8Figure 11-7 +VREF Bo (LSB) 2 R 2 R R B₁ 2 R R - B₂ 2 R R www B3 (MSB) 2 R OUT VOUT R -VREF 16 XB VOUT
The control of a positioning device may be achieved using a servomotor, which is a motor designed to drive a mechanical device as long as an error signal exists. Figure 11-35 shows a simple servo- controlled system that is controlled by a digital input that could be coming directly from a computer
An eight-bit DAC has a full-scale error of 0.2% F.S. If the DAC has a full-scale output of 10 mA, what is the most that it can be in error for any digital input? If the D/A output reads 50 μA for a digital input of 00000001, is this within the specified range of accuracy? (Assume no offset error.)
(a) Define binary-weighted resistor network.(b) Define R/2R ladder network.(c) Define DAC settling time.(d) Define full-scale error.(e) Define offset error.
A particular six-bit DAC has a full-scale output rated at 1.260 V. Its accuracy is specified as ±0.1% F.S., and it has an offset error of ±1 mV. Assume that the offset error has not been zeroed out. Consider the measurements made on this DAC (Table 11-10), and determine which of them are not
What is the purpose of running the unknown signal through a pulse shaper?
What are the units of a frequency measurement?
What does the display show during the sample interval?
What are the names of the functional blocks in level 2 of the microwave oven hierarchy?
Describe the signal that drives the clock input to the minutes/seconds timer whenever no buttons on the keypad are being pressed.
Describe the signal that drives the clock input to the minutes/seconds timer whenever any buttons on the keypad are being pressed.
What is being defined at the top level of a hierarchical design?
Where does the design process start?
Where does the building process start?
At which stage(s) should simulation testing be done?
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![LEMAFETO GONNA 1 2 3 4 5 6 7 8 9 10 11 12 SUBDESIGN fig9_69 ( a[3..0], b[3..01 agtb, altb, aeqb > BEGIN IF :](https://dsd5zvtm8ll6.cloudfront.net/images/question_images/1700/2/2/3/2616557591d2c4121700223262884.jpg)
