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digital systems principles and application

Digital Systems Principles And Application 12th Edition Ronald Tocci, Neal Widmer, Gregory Moss - Solutions

Modify the VHDL code in Figure 6-24 to create a 4-bit parallel adder.Figure 6-24 900260 GAWNH 2 4 ENTITY fig6_24 IS PORT ( 10 a b S : IN INTEGER RANGE 0 TO 255; :IN INTEGER RANGE 0 TO 255; :OUT INTEGER RANGE 0 TO 511 6 ); 7 END fig6_24; ARCHITECTURE parallel OF fig6_24 IS 11 BEGIN 12 13 END
Represent 13510 and 26510 in BCD and then perform BCD addition. Check your work by converting the result back to decimal.
The Accumulator and B are registers. What fundamental block makes up these registers?
In AHDL, where are constants defined? Where are they defined in VHDL?
Assume the following input levels in Figure 6-6: A4 A3 A2 A1A0 = 01001; B4 B3 B2B1B0 = 00111; C0 = 0.(a) What are the logic levels at the outputs of FA #2?(b) What is the logic level at the C5 output?Figure 6-6 S4 B FA #4 C4 S3 FA # 3 SV FA # 2 S₁ FA #1 Sum appears at S4, S3, S₂, S₁, So
Represent each of the following signed decimal numbers in the 2’s-complement system. Use a total of eight bits, including the sign bit. (a)* +32 (b)*-14 (c)* +63 (d)* -104 (e)* +127 (f)* -127 (g)* +89 (h)* -55 (i) -1 (j) - 128 (k) +169 (1) 0 (m) +84 (n) +3 (0) -3 (p) -190
Each of the following numbers is a five-bit signed binary number in the 2’s-complement system. Determine the decimal value in each case:(a) 01100 (b) 11010 (c) 10001
Determine the contents of the A register after the following sequence of operations: [A] = 0000, [0110] → [B], [S] → [A], [1110] → [B], [S] → [A].
What will be the logic level at C4 in Example 6-10 ?Data from Example 6-10Determine the logic levels at the inputs and outputs of the eight-bit adder in Figure 6-11(b) when 7210 is added to 13710.Figure 6-11(b) Cg 8-bit augend A7 A6 A5 A4 74HC283 (high-order adder) By B6 B5 B4 C4 Σ7 16 15 14 13 12
How can an adder operate at higher frequencies?
Repeat question 2 for ADD = 0, SUB = 1.Data from Question 2Assume that [A] = 0011 and [B] = 0010 in Figure 6-14. If ADD = 1 and SUB = 0, determine the logic levels at the OR gate outputs.Figure 6-14 Transfer pulse BB₂ 0 12 B3 CLK Ag { B₂ B₂ 6 D B register 11 B₂ 01 CLK A₂ A₂ B₁
Change the select code to 110, and repeat review question 1.Data from question 1Apply the following inputs to the ALU of Figure 6-15, and determine the outputs: S2S1S0 = 001, A3A2A1A0 = 1110, B3B2B1B0 = 1001, CN = 1.Figure 6.15 A B S Inputs A3 B3 B₂ B₁ Bo CN S₁ So 74LS382/ 74HC382 A = 4-bit
What range of signed decimal values can be represented in 12 bits (including the sign bit)?
In AHDL, the following object is declared: toggles[7..0] :INPUT. Give an expression for the least significant four bits using AHDL syntax.
Which of the following hex numbers represent positive values: 2F, 77EC, C000, 6D, FFFF?
Why is the A register called an accumulator?
Why are constants useful?
Each of the following numbers represents a signed decimal number in the 2’s-complement system. Determine the decimal value in each case.(a) 01101(b) 11101(c) 01111011(d) 10011001(e) 01111111(f) 10000000(g) 11111111(h) 10000001(i) 01100011(j) 11011001
What is the range of unsigned decimal values that can be represented in a byte?
True or false: When the adder/subtractor circuit is used for subtraction, the 2’s complement of the subtrahend appears at the input of the adder.
Apply the following inputs to the circuit of Figure 6-16, and determine the outputs: B = 01010011, A = 00011000.Figure 6-16 By B Bg B4 S₂ S₁ So CN B3 B₂ B₁ Bo A₂ A₂ A₁ A₂ 74HC382 Ay A6 A₂ A₂ CN4 OVR F3 F₂ F₁ Fo 27 26 25 24 Notes: Z1 adds lower-order bits. 22 adds
How many bits are required to represent decimal values ranging from –50 to +50 ?
In VHDL, the following object is declared: toggles :IN BIT_VECTOR (7 DOWNTO 0). Give an expression for the least significant four bits using VHDL syntax.
If the constant max_val has a value of 127, how will a compiler interpret the expression max_val -5?
(a) What range of signed decimal values can be represented using 12 bits, including the sign bit?(b) How many bits would be required to represent decimal numbers from –32,768 to +32,767?
What is the range of signed decimal values that can be represented in a byte?
Change the select code to 111, and repeat review question 4.Data from Question 4Apply the following inputs to the circuit of Figure 6-16, and determine the outputs: B = 01010011, A = 00011000.Figure 6-16 By B Bg B4 S₂ S₁ So CN B3 B₂ B₁ Bo A₂ A₂ A₁ A₂ 74HC382 Ay A6 A₂ A₂ CN4 OVR
What is the largest negative decimal value that can be represented by a two-byte number?
What would be the result of ORing the two registers of Example 6-15?Data from Example 6-15 Assume D3, D2, D₁, Do has the value 1011 and G3, G2, G₁, Go has the value 1100. Let's define D = [D3, D2, D₁, Dol and G = [G3, G2, G₁, Gol. Let's also define Y = [Y3, Y2, Y₁, Yol where Y is related
List, in order, all of the signed numbers that can be represented in five bits using the 2’s-complement system.
A certain computer is storing the following two signed numbers in its memory using the 2’s-complement system:While executing a program, the computer is instructed to convert each number to its opposite sign; that is, change the +31 to –31 and change the –12 to +12. How will it do this?
Perform the 2’s-complement operation on each of the following.(a) 10000 (b) 10000000 (c) 1000
How many 74HC382s are needed to add two 32-bit numbers?
Write an HDL statement that would OR the two objects d and g together. Use your favorite HDL.
Represent each of the following decimal values as an eight-bit signed binary value. Then negate each one.(a) +73 (b) –12 (c) +15 (d) –1 (e) –128 (f) +127
Add the hex numbers 58 and 24.
Define the negation operation.
Write an HDL statement that would XOR the two most significant bits of d with the two least significant bits of g and put the result in the middle two bits of x.
Add the hex numbers 58 and 4B.
(a) What is the range of unsigned decimal values that can be represented in 10 bits? What is the range of signed decimal values using the same number of bits?(b) Repeat both problems using eight bits.
Perform the following operations in the 2’s-complement system. Use eight bits (including the sign bit) for each number. Check your results by converting the binary result back to decimal. (a)* Add +9 to +6. (b)* Add +14 to -17. (c)* Add +19 to -24. (d)* Add -48 to -80. (e)* Subtract +16 from
The reason why the sign-magnitude method for representing signed numbers is not used in most computers can readily be illustrated by performing the following.(a) Represent +12 in eight bits using the sign-magnitude form.(b) Represent –12 in eight bits using the sign-magnitude form.(c) Add the two
Determine the logic levels at the inputs and outputs of the eight-bit adder in Figure 6-11(b) when 7210 is added to 13710.Figure 6-11(b) 8 8-bit augend A7 As A5 A4 74HC283 (high-order adder) By B6 B5 B4 C4 Σε Σε Σε Σε Σ3 Σε Σε Σο A3 A₂ A₁ A₂ 8-bit addend B3 B₂ B₁
Repeat Problem 6-9 for the following cases, and show that overflow occurs in each case.(a) Add +37 to +95.(b) Subtract +37 from –95.(c) Add -37 to –95.(d) Subtract –37 from +95.Data from Problem 6-9Perform the following operations in the 2’s-complement system. Use eight bits (including the
(a) Determine the 74HC382 outputs for the following inputs: S2S1S0 = 010, A3A2A1A0 = 0100, B3B2B1B0 = 0001, and CN = 1.(b) Change the select code to 011 and repeat.
Multiply the following pairs of binary numbers, and check your results by doing the multiplication in decimal.(a) 111 × 101(b) 1011 × 1011(c) 101.101 × 110.010(d) .1101 × .1011(e) 1111 × 1011(f) 10110 × 111
How would the arrangement of Figure 6-16 have to be changed in order to perform the subtraction (B – A)?Figure 6-16 By B Bg B₂ 74HC382 Ay As As A₂ S₂ S₁ So CN Bg B₂ B₁ Bo A₂ A₂ A₁ A CN4 OVR F₁ F₂ F₁ Fo • Notes: Z1 adds lower-order bits. Z2 adds higher-order bits. 8-bit
Perform the following divisions. Check your results by doing the division in decimal.(a) 1100 ÷ 100(b) 111111 ÷ 1001(c) 10111 ÷ 100(d) 10110.1101 ÷ 1.1(e) 1100011 ÷ 1001(f) 100111011 ÷ 1111
Consider again the adder/subtractor circuit. Suppose that there is a break in the connection path between the SUB input and the AND gates at point X in Figure 6-17. Describe the effects of this open on the circuit operation for each mode.Figure 6-17 C4 BB₂ 100 8 12 7 Ag B₂ B₂ B₂ 6 11 5 B₁
Add the following decimal numbers after converting each to its BCD code.(a) 74 + 23(b) 58 + 37(c) 147 + 380(d) 385 + 118(e) 998 + 003(f) 623 + 599(g) 555 + 274(h) 487 + 116
Find the sum of each of the following pairs of hex numbers.(a) 3E91 + 2F93(b) 91B + 6F2(c) ABC + DEF(d) 2FFE + 0002(e) FFF + 0FF(f) D191 + AAAB(g) 5C74 + 22BA(h) 39F0 + 411F
Create a mod-8 down counter using a block symbol for the register and an LPM block for the subtractor.
Perform the following subtractions on the pairs of hex numbers.(a) 3E91 – 2F93(b) 91B – 6F2(c) 0300 – 005A(d) 0200 – 0003(e) F000 – EFFF(f) 2F00 – 4000(g) 9AE5 – C01D(h) 4321 – F165
Assume D3, D2, D1, D0 has the value 1011 and G3, G2, G1, G0 has the value 1100. Let’s define D = [D3, D2, D1, D0] and G = [G3, G2, G1, G0]. Let’s also define Y = [Y3, Y2, Y1, Y0] where Y is related to D and G as follows:Y = D · G;What is the value of Y after this operation?
The owner’s manual for a small microcomputer states that the computer has usable memory locations at the following hex addresses: 0200 through 03FF, and 4000 through 7FD0. What is the total number of available memory locations?
For the register values described in Example 6-15, declare each d, g, and y. Then write an expression using your favorite HDL that performs the ANDing operation on all bits.Data from Example 6-15Assume D3, D2, D1, D0 has the value 1011 and G3, G2, G1, G0 has the value 1100. Let’s define D = [D3,
Convert the FA circuit of Figure 6-8 to all NAND gates.Figure 6-8 A B CN 1 기 FAI S COUT
(a) A certain eight-bit memory location holds the hex data 77. If this represents an unsigned number, what is its decimal value?(b) If this represents a signed number, what is its decimal value?(c) Repeat (a) and (b) if the data value is E5.
A full adder can be implemented in many different ways. Figure 6-27 shows how one may be constructed from two half adders. Construct a function table for this arrangement, and verify that it operates as a FA.Figure 6-27 B CARRY IN HA SUM CARRY Full adder HA CARRY SUM CARRY OUT
Write the function table for a half adder (inputs A and B; outputs SUM and CARRY). From the function table, design a logic circuit that will act as a half adder.
Refer to Figure 6-10. Determine the contents of the A register after the following sequence of operations: [A] = 0000, [0100] → [B], [S] → [A], [1011] → [B], [S] → [A].Figure 6-10
Refer to Figure 6-10. Assume that each FF has tPLH = tPHL = 30 ns and a setup time of 10 ns, and that each FA has a propagation delay of 40 ns. What is the minimum time allowed between the PGT of the LOAD pulse and the PGT of the TRANSFER pulse for proper operation?Figure 6-10
In the adder and subtractor circuits discussed in this chapter, we gave no consideration to the possibility of overflow. Overflow occurs when the two numbers being added or subtracted produce a result that contains more bits than the capacity of the accumulator. For example, using four-bit
Add the necessary logic circuitry to Figure 6-10 to accommodate the transfer of data from memory into the A register. The data values from memory are to enter the A register through its D inputs on the PGT of the first TRANSFER pulse; the data from the sum outputs of the FAs will be loaded into A
Design a look-ahead carry circuit for the adder of Figure 6-10 that generates the carry C3 to be fed to the FA of the MSB position based on the values of A0, B0, C0, A1, B1, A2, and B2. In other words, derive an expression for C3 in terms of A0, B0, C0, A1, B1, A2, and B2. (Begin by writing the
Show the logic levels at each input and output of Figure 6-11(b) when EC16 is added to 4316.Figure 6-11(b) C8 8-bit augend A7 A6 A5 A4 74HC283 (high-order adder) By B6 B5 B4 A3 A2 A₁ A B3 B₂ B₁ Bo 8-bit addend 74HC283 (low-order adder) (b) Co
For the circuit of Figure 6-14, determine the sum outputs for the following cases.(a) A register = 0101 (+5), B register = 1110 (–2); SUB = 1, ADD = 0 (b) A register = 1100 (–4), B register = 1110(–2); SUB= 0,ADD = 1 (c) Repeat (b) with ADD = SUB = 0.Figure 6-14 Transfer pulse 8 B₂B₂
For the circuit of Figure 6-14 determine the sum outputs for the following cases.(a) A register = 1101 (-3), B register = 0011 (+3); SUB = 1, ADD = 0.(b) A register = 1100 (-4), B register = 0010 (+2); SUB = 0, ADD = 1.(c) A register = 1011 (-5), B register = 0100 (+4); SUB = 1, ADD = 0.Figure 6-14
For each of the calculations of Problem 6-27, determine if overflow has occurred.Data from Problem 6-27For the circuit of Figure 6-14, determine the sum outputs for the following cases.(a) A register = 0101 (+5), B register = 1110 (–2); SUB = 1, ADD = 0 (b) A register = 1100 (–4), B register =
For each of the calculations of Problem 6-28, determine if overflow has occurred.Data from Problem 6-28For the circuit of Figure 6-14 determine the sum outputs for the following cases.(a) A register = 1101 (-3), B register = 0011 (+3); SUB = 1, ADD = 0.(b) A register = 1100 (-4), B register = 0010
Show how the gates of Figure 6-14 can be implemented using three 74HC00 chips.Figure 6-14 Transfer pulse 8 B₂B₂ B₂ B₂ D 12 7 B₂ CLK A3 Im A3 6 D B register 11 5 B₂ CLK A₂ A₂ D 10 B₁ 3 74LS283 A₁ A₁ CLK BoBo 2 D Bo CLK A A₂ ADD SUB 44 45 Col
Modify the circuit of Figure 6-14 so that a single control input, X, is used in place of ADD and SUB. The circuit is to function as an adder when X = 0, and as a subtractor when X = 1. Then simplify each set of gates.Figure 6-14 Transfer pulse 8 B₂B₂ B₂ B₂ D 12 7 B₂ CLK A3 Im A3 6 D B
Determine the F, CN+4, and OVR outputs for each of the following sets of inputs applied to a 74LS382. (a)* [S] = 011, [A] = 0110, [B] = 0011, CN = 0 (b) [S] = 001, [A] = 0110, [B] = 0011, CN = 1 (c) [S] = 010, [A] = 0110, [B] = 0011, CN = 1
Determine the Σ outputs in Figure 6-16 for the following sets of inputs.(a)*[S] = 110, [A] = 10101100, [B] = 00001111 (b) [S] = 100, [A] = 11101110, [B] = 00110010Figure 6-16 By Bg B5 B4 74HC382 A, CN+4 OVR F3 F₂ F₁ Fo ● S₂ S₁ So CN Bg B₂ B₁ Bo Ag A₂ A₁ A₂ jo to do Notes: 21
Show how the 74HC382 can be used to produce [F] = [A̅].
Add the necessary logic to Figure 6-16 to produce a single HIGH output whenever the binary number at A is exactly the same as the binary number at B. Apply the appropriate select input code (three codes can be used).Figure 6-16 By Bg B5 B4 74HC382 A, CN+4 OVR F3 F₂ F₁ Fo ● S₂ S₁ So CN Bg
Consider the circuit of Figure 6-10. Assume that the A2 output is stuck LOW. Follow the sequence of operations for adding two numbers, and determine the results that will appear in the A register after the second TRANSFER pulse for each of the following cases. Note that the numbers are given in
A technician breadboards the adder/subtractor of Figure 6-14. During testing, she finds that whenever an addition is performed, the result is 1 more than expected, and when a subtraction is performed, the result is 1 less than expected. What is the likely error that the technician made in
Describe the symptoms that would occur at the following points in the circuit of Figure 6-14 if the ADD and SUB lines were shorted together.(a) B[3..0] inputs of the 74LS283 IC(b) C0 input of the 74LS283 IC(c) SUM (Σ) [3..0] outputs(d) C4Figure 6-14 Transfer pulse 8 B₂B₂ B₂
Functionally simulate (with 15 test cases) the 8-bit adder given in:(a) Figure 6-19(a) (b) Figure 6-19(b)Figure 6-19 A[8.. 1] B[8..1] A[8..1] B[8.. 1] INPUT GND INPUT INPUT INPUT A[8..
Design a mod-16 binary, up/down counter using LPM_FF and LPM_ ADD_SUB megafunctions. The count direction will be controlled by an input named UP_DN. Functionally simulate your design to verify that it operates correctly.
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Refer to Problem 6-23. Modify the code of Figure 6-23 or Figure 6-24 to add an overflow output.Figure 6-23Figure 6-24Data from Problem 6-23In the adder and subtractor circuits discussed in this chapter, we gave no consideration to the possibility of overflow. Overflow occurs when the two numbers
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Modify Figure 6-23 or Figure 6-24 to make it a 12-bit adder without using constants.Figure 6-23Figure 6-24 123 10 10 5 6 7 8 9 10 11 4 b[7..0] 23 12 SUBDESIGN fig6_23 13 14 ( a [7..0] s [8..0] ) : INPUT; : INPUT; : OUTPUT: VARIABLE aa [8..0] bb [8..0] BEGIN aa [8..0] = (GND, a [7..0]); bb
Problems 6-42 through 6-47 deal with the same two arrays, a and b, which we will assume have been defined in an HDL source file and have the following values: [a] = [10010111], [b] = [00101100]. Output array [z] is also an eight-bit array. Answer Problems 6-42 through 6-47 based on this
Modify Figure 6-23 or Figure 6-24 to make it a versatile n-bit adder module with a constant defining the number of bits.Figure 6-23Figure 6-24 123 10 10 5 6 7 8 9 10 11 4 b[7..0] 23 12 SUBDESIGN fig6_23 13 14 ( a [7..0] s [8..0] ) : INPUT; : INPUT; : OUTPUT: VARIABLE aa [8..0] bb [8..0] BEGIN aa
Write an HDL file to create the equivalent of a 74382 ALU without using a built-in macrofunction.
Define each of the following terms.(a) Full adder(b) 2’s complement(c) Arithmetic/logic unit(d) Sign bit(e) Overflow(f) Accumulator(g) Parallel adder(h) Look-ahead carry(i) Negation(j) B register
In a typical microprocessor ALU, the results of every arithmetic operation are usually (but not always) transferred to the accumulator register, as in Figures 6-10 and 6-14. In most microprocessor ALUs, the result of each arithmetic operation is also used to control the states of several special
In working with microcomputers, it is often necessary to move binary numbers from an eight-bit register to a 16-bit register. Consider the numbers 01001001 and 10101110, which represent +73 and –82, respectively, in the 2’s-complement system. Determine the 16-bit representations for these
Compare the eight- and 16-bit representations for +73 from Problem 6-54. Then compare the two representations for –82. There is a general rule that can be used to convert easily from eight-bit to 16-bit representations. Can you see what it is? It has something to do with the sign bit of the
Add another flip-flop, E, to the counter of Figure 7-1. The clock signal is an 8-MHz square wave.(a) What will be the frequency at the E output? What will be the duty cycle of this signal?(b) Repeat (a) if the clock signal has a 20% duty cycle.(c) What will be the frequency at the C output?(d) What
Which control input signal holds the highest priority for each of the oneshot descriptions?
How many gates are needed to decode a six-bit counter fully?
Why is it desirable to avoid having asynchronous controls on counters?
List the six steps in the procedure for designing a synchronous counter.

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