New Semester
Started
Get
50% OFF
Study Help!
--h --m --s
Claim Now
Question Answers
Textbooks
Find textbooks, questions and answers
Oops, something went wrong!
Change your search query and then try again
S
Books
FREE
Study Help
Expert Questions
Accounting
General Management
Mathematics
Finance
Organizational Behaviour
Law
Physics
Operating System
Management Leadership
Sociology
Programming
Marketing
Database
Computer Network
Economics
Textbooks Solutions
Accounting
Managerial Accounting
Management Leadership
Cost Accounting
Statistics
Business Law
Corporate Finance
Finance
Economics
Auditing
Tutors
Online Tutors
Find a Tutor
Hire a Tutor
Become a Tutor
AI Tutor
AI Study Planner
NEW
Sell Books
Search
Search
Sign In
Register
study help
computer science
digital systems principles and application
Digital Systems Principles And Application 12th Edition Ronald Tocci, Neal Widmer, Gregory Moss - Solutions
For each item, indicate whether it is referring to a decoder or an en-coder.(a) Has more inputs than outputs.(b) Is used to convert key actuations to a binary code.(c) Only one output can be activated at one time.(d) Can be used to interface a BCD input to an LED display.(e) Often has driver-type
An extremely important principle of troubleshooting, called divide-and conquer, was introduced. It is really not about military strategy, but rather describes the most efficient way to eliminate from consideration all the parts of the circuit that are working correctly. Assume that data have been
Determine the output levels for the 74147 encoder when A̅8 = A̅4 = 0 and all other inputs are HIGH.
Apply the signals of Figure 9-75 to the inputs of a 74147 as follows:Draw the waveforms for the encoder’s outputs.Figure 9-75 A → A B → A4 C-A₂ D→ A₁
Figure 9-76 shows the block diagram of a logic circuit used to control the number of copies made by a copy machine. The machine operator selects the number of desired copies by closing one of the selector switches S1 to S9. This number is encoded in BCD by the encoder and is sent to a comparator
The keyboard circuit of Figure 9-16 is designed to accept a three digit decimal number. What would happen if four digit keys were activated (e.g., 3095)? Design the necessary logic to be added to this circuit so that after three digits have been entered, any additional digits will be ignored until
Convert 01010010 (BCD for decimal 52) to binary. Repeat for 10010101 (decimal 95).
A technician breadboards the keyboard entry circuit of Figure 9-16 and tests its operation by trying to enter a series of three-digit numbers. He finds that sometimes the digit 0 is entered instead of the digit he pressed. He also observes that it happens with all of the keys more or less randomly,
The BCD representation for decimal 56 is applied to the converter of Figure 9-43. Determine the Σ outputs from each adder and the final binary output.Figure 9-43 D₁ C₁ B₁ A₁ Do Co Bo Ao 3210 C₁74HC83 |||| Co 3 2 4 6 Σ. Σ. Σ. Σ BCD representation 3210 C₂i i 11 3 21 6 ΣΣ
Without referring back to the text, repeat the design of a Full adder and a Half Adder circuit.
Subtract 67F – 2A4.
Add 3AF to 23C.
Subtract 3A516 from 59216.
Describe the function of the inputs L̅O̅A̅D̅ and D, C, B, A.
When designing a counter with D flip-flops, what is applied to the D inputs in order to drive it to the NEXT state on the next active clock edge?
A counter is needed that will count the number of items passing on a conveyor belt. A photocell and light source combination is used to generate a single pulse each time an item crosses its path. The counter must be able to count as many as one thousand items. How many FFs are required?
A certain J-K flip-flop has tpd = 12 ns. What is the largest MOD counter that can be constructed from these FFs and still operate up to 10 MHz?
What is a bus and how is it represented in a graphical block diagram design file in Altera?
Which shift-register counter requires the most decoding circuitry?
How many logic devices are required for a MOD-64 parallel counter?
True or false: All BCD counters are decade counters.
Complete the timing diagram in Figure 7-104 for a 74ALS162 with the indicated input waveforms applied. Assume the initial state is 0000.Figure 7-104 CLK CLR LOAD ENT ENP DCBA QD QC QB QA RCO דז M L 1 L -F TI bo 8 L II F+ SE -F LJ L I --- I 1-T- J_L_ :חדר 111_
How would you write the HDL description to trigger a storage device (flip-flop) on a falling edge instead of a rising edge of the clock?
A technician receives a “trouble ticket” for a circuit board that says the variable frequency divider operates “sometimes.” Sounds like a dreaded intermittent fault problem—often the hardest problems to find! His first thought is to send it back with the note “Use only when operating
Draw a schematic to create a recycling, MOD-6 counter that uses:(a) the clear control on a 74ALS160(b) the clear control on a 74ALS162
Repeat Problem 7-37 for Figure 7-110(b).Data from Problem 7-37Analyze the synchronous counter in Figure 7-110(a). Draw its timing diagram and determine the counter’s modulus.Figure 7-110(a)Figure 7-110(b) D D CLK CLR O J CLK K с ē CLK O K CLR (a) B B J CLKO K CLR J CLKO K CLR
Repeat Example 7-20 for the input waveforms given in Figure 7-116.Data from Example 7-20A shift register is often used as a way to delay a digital signal by an integral number of clock cycles. The digital signal is applied to the shift register’s serial input and is shifted through the shift
Simulate the universal shift-register design from Example 7-27.Data from Example 7-27Suppose we want to design a universal four-bit shift register, using HDL, that has four synchronous modes of operation: Hold Data, Shift Left, Shift Right, and Parallel Load. Two input bits will select the
Create an eight-bit universal shift register by cascading two of the modules in Example 7-27. Simulate the design.Data from Example 7-27Suppose we want to design a universal four-bit shift register, using HDL, that has four synchronous modes of operation: Hold Data, Shift Left, Shift Right, and
Define each of the following: VOH, VIL, IOL, IIH, tPLH, tPHL, ICCL, ICCH.
Describe the operation of a CMOS bilateral switch.
What must be done to interface a standard TTL output to a 74AC or a 74HC input? Assume VDD = +5 V.
What is the function of an interface circuit?
True or false: A TTL output acts as a current sink in the LOW state.
What causes the output of a comparator to go to the HIGH logic state?
What is the function of a logic pulser?
What is the maximum current that 74ALS00 can deliver to a load while maintaining a valid logic 1 on its output?
Two different logic circuits have the characteristics shown in Table 8-14.(a) Which circuit has the best LOW-state DC noise immunity? The best HIGH-state DC noise immunity?(b) Which circuit can operate at higher frequencies?(c) Which circuit draws the most supply current?Table 8-14 Vsupply
(a) Which TTL series is the best at high frequencies?(b) Which TTL series has the largest HIGH-state noise margin?(c) Which series has essentially become obsolete in new designs?(d) Which series uses a special diode to reduce switching time?(e) Which series would be best for a battery-powered
What factors determine the IOL(max) rating of a device?
The input/output voltage specifications for the standard TTL family are listed in Table 8-1. Use these values to determine the following.(a) The maximum-amplitude noise spike that can be tolerated when a HIGH output is driving an input.(b) The maximum-amplitude noise spike that can be tolerated
What will be the logic output of a TTL NAND gate that has all of its inputs unconnected?
Which value below is closest to the drain to source resistance of a MOSFET that is turned ON? 1 ohm, 1 kilo-ohm, 1 mega-ohm, 1 giga-ohm
How does CMOS internal circuitry differ from N-MOS?
Which CMOS series is pin-compatible with TTL?
What are the two advantages of higher-density ICs?
When does a HIGH/LOW conflict occur?
What are the three possible states of a tristate output?
How close together do components need to be to ignore “transmission line” effects?
True or false: If a logic circuit has a fan-out of 5, the circuit has five outputs.
True or false: There is no TTL bilateral switch.
What is usually the problem with CMOS driving TTL?
True or false: All CMOS outputs can drive TTL in the HIGH state.
In which TTL input state does the largest amount of input current flow?
What causes the output of a comparator to go to the LOW logic state?
True or false: A logic pulser will produce a voltage pulse at any node.
What is the highest valid voltage that a 74ALS00 will interpret as a logic 0 on its inputs?
Look up the IC data sheets, and use maximum values to determine PD(avg) and tpd(avg) for one gate on each of the following TTL ICs. (See Example 8-2 in Section 8-3.)(a)* 7432 (b)* 74S32 (c) 74LS20 (d) 74ALS20 (e) 74AS20Data from Example 8-2Refer to the data sheet for the 74ALS00 quad two-input
Assuming the same cost for each, why should you choose to use a 74ALS193 counter over a 74LS193 or a 74AS193 in a circuit operating from a 40-MHz clock?
How many 7407 inputs can a 74AS chip drive?
Refer to the data sheet for the 74ALS00 quad two-input NAND IC in Figure 8-11. Determine the maximum average power dissipation and the maximum average propagation delay of a single gate.Figure 8-11 Recommended Operating Conditions Supply voltage High-level input voltage Low-level input
What are two acceptable ways to handle unused inputs to an AND gate?
Which value below is closest to the drain to source resistance of a MOSFET that is turned OFF?1 ohm, 1 kilo-ohm, 1 mega-ohm, 1 giga-ohm
How many P-channel MOSFETs are in a CMOS INVERTER?
Which CMOS series is electrically compatible with TTL?
What are the drawbacks?
Why shouldn’t totem-pole outputs be tied together?
What is the state of a tristate output when it is disabled?
What three characteristics of real wires add up to distort signals that move through them?
True or false: The HIGH-stage noise margin is the difference between VIH(min) and VCC.
True or false: Any CMOS output can drive any single TTL input.
State the advantages and disadvantages of a totem-pole output.
Is an LM339 output more similar to a TTL totem-pole or an open-collector output?
True or false: A logic pulser can force a node LOW or HIGH for extended periods of time.
Identify the pull-up and pull-down transistors for the 74S circuit in Figure 8-12.Figure 8-12 Schottky diode (a) Inputs -11 D₁ a · 2.8 ΚΩ D₂ (b) Vcc 760 Ω Q3 370 Ω 3.5 ΚΩ 350 Ω 411 55 Ω -Output
How long (max) will it take for the output of a 74ALS00 to go HIGH after its input goes LOW?
What can happen if a TTL output is connected to more gate inputs than it is rated to handle?
Use Table 8-6 to calculate the DC noise margins for a typical 74LS IC. How does this compare with the standard TTL noise margins?Table 8-6 Performance ratings Propagation delay (ns) Power dissipation (mW) Max. clock rate (MHz) Fan-out (same series) Voltage parameters VOH(min) (V) VOL(max)
How many MOSFETs are in a three-input CMOS NAND gate?
Which CMOS series is functionally equivalent to TTL?
A certain logic family has the following voltage parameters:(a) What is the largest positive-going noise spike that can be tolerated?(b) What is the largest negative-going noise spike that can be tolerated? VIH (min) = 3.5 V VOH (min) = 4.9 V VIL(max) = 1.0 V VOL(max) = 0.1 V
Repeat question 2 for a NOR gate.Data from Question 2What are two acceptable ways to handle unused inputs to an AND gate?
Which fundamental electrical component does the gate of a MOSFET represent?
What is the minimum HIGH voltage at a 74LVT input?
How do open-collector outputs differ from totem-pole outputs?
What is bus contention?
What is the purpose of bus terminations?
Describe the difference between current sinking and current sourcing.
Which CMOS series can TTL drive without a pull-up resistor?
Which TTL transistor is the pull-up transistor in the NAND circuit?
How does a logic probe respond to the logic pulser?
What is the maximum current drawn from the power supply of a 74ALS00 IC if all of its outputs are LOW?
How many 74S112 CP inputs can be driven by a 74LS04 output? By a 74F00 output?
For each statement, indicate the term or parameter being described.(a) Current at an input when a logic 1 is applied to that input(b) Current drawn from the VCC source when all outputs are LOW(c) Time required for an output to switch from the 1 to the 0 state(d) The size of the voltage spike that
True or false: When NAND gate inputs are tied together, they are always treated as a single load on the signal source.
Refer to the data sheet for the 74LS112 J-K flip-flop.(a) Determine the HIGH and LOW load current at the J and K inputs.(b) Determine the HIGH and LOW load current at the clock and clear inputs.(c) How many 74LS112 clock inputs can the output of one 74LS112 drive?
In Figure 8-62(b), the 7406 output is used to switch current to a relay.(a) What voltage will be at the 7406 output when Q = 0?(b) What is the largest current relay that can be used?(c) How can we modify this circuit to use a 7407?Figure 8-62 68 ΚΩ CONTROL +5 V 74HC4016 · 22 ΚΩ = VOUT
Determine the approximate values of VOUT for both states of the CONTROL input in Figure 8-62.Figure 8-62 68 ΚΩ CONTRO L→ +5V 74HC4016 · 22 ΚΩ VOUT
Determine the gain of the op-amp circuit of Figure 8-64 for the two states of the GAIN SELECT input. This circuit shows the basic principle of digitally controlled signal amplification.Figure 8-64 VIN GAIN SELECT 100 ΚΩ 100 ΚΩ w 74HC4016 100 ΚΩ VOUT
Determine the waveform at output X in Figure 8-63 for the given input waveforms. Assume that RON ≈ 200Ω for the bilateral switch.Figure 8-63 eN 10 k www 74HC4016 74HC4016 1|ww X R₁-10 kn en C 2 V OV 5 V OV ли прир
Showing 500 - 600
of 1612
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Last
Step by Step Answers
Get 50% OFF
Claim Now
