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computer science
digital systems principles and application
Digital Systems Principles And Application 12th Edition Ronald Tocci, Neal Widmer, Gregory Moss - Solutions
What is a look-up table?
What major advantage does a hardware design solution have over a software solution?
What advantage does SRAM programming technology have over EEPROM?
Describe each of the following four ASIC subcategories:(a) PLDs(b) Gate arrays(c) Standard-cell(d) Full-custom
What are HCPLDs?
Name two advantages of GAL devices over PAL devices.
What disadvantage does SRAM programming technology have compared to EEPROM?
What are the major advantages and disadvantages of a full-custom ASIC?
What are two major differences between CPLDs and FPGAs?
Name the six PLD programming technologies. Which is one-time programmable? Which is volatile?
What does volatility refer to?
How is the programming of SRAM-based PLDs different from other programming technologies?
Describe the functions of each of the following architectural structures found in the Altera MAX7000S family:(a) LAB (b) PIA (c) Macrocell
What two ways can be used to program the MAX7000S family devices?
What standard device interface is used for in-system programming in the MAX7000S family?
What is an LUT in the MAX II family?
Differentiate between the logic block structures that are used to produce a combinational function in the MAX7000S and MAX II families.
What type of programming technology is used in the LEs of the MAX II family?
How does a MAX II CPLD accomplish “instant on” at power-up in an application?
What are the four types of ASICs?
How would the equation for the output of O1 in Figure 13-5(b) change if all the fuses from AND gate 14 were left intact?Figure 13.5(b) 03 - AB+CD; 0₂ - ABC 0₁ - ABCD + ABCD; O-A+BD + CD 3 (b) 6 8 9 10 11 12 13 14 15 Blown fuse DCBA 03 0₂ 01 00. DCBA DCBA *
What does a dot represent on a PLD diagram?
True or false: A PROM stores a logic 1 when its fusible link is intact.
Why is “page mode” faster?
What functions does a DRAM controller perform?
Outline the steps that occur when the CPU writes to memory.
What is the capacity of a memory that has 16 address inputs, four data inputs, and four data outputs?
What is the function of the memory enable input?
How many address inputs would there be on a 1M × 1 DRAM chip?
Which type of RAM would you expect to find on the main memory modules of your PC?
Explain the difference between the read (fetch) and write (store) operations.
What device places data on the data bus during a read cycle?
How many pins are required for a 64K × 4 RAM with one CS input, one R/W̅ control input, power, ground, and common I/O?
Describe the conditions at each input and output when the contents of address location 00100 are to be read. Refer to Figure 12-4.Figure 12-4 0100 0110 1001 1 1 1 1 0|1|0|0 0001 0000 ⠀⠀⠀⠀ 1101 1 1 0 1 0 1 1 1 (a) WRITING the data word 0100 into memory location
What does FIFO mean?
How many are needed for a 64K × 16 module?
What is the main advantage of flash memory over EEPROMs?
What type solid-state memory technology shows promise of replacing many existing technology as a “universal memory”?
How does a PROM differ from an MROM? Can it be erased and reprogrammed?
Which timing specification defines the minimum time from when the CPU puts out a new address until the end of the RD pulse?
What is the function of a refresh counter?
Describe the function of the row-select decoder, the column-select decoder, and the output buffers in the ROM architecture.
Describe the procedure for reading from ROM.
Which signal in Figure 12-27(b) makes sure that the correct portion of the complete address appears at the DRAM inputs?Figure 12-27(b) CPU A15 A14 A13 A12 A₁1 A10 Ag Ag A7 As As A4 A3 A₂ A₁ A Multi- plexer AA8 A₁/Ag A₂/A 10 64K A/A₁1 DRAM A4/A12 Ag/A13 Ag/A 14 A7/A15 WE RAS MUX* *MUX =
Outline the steps that take place when the CPU reads from memory.
How many different addresses are required by the memory of Problem 12-1?Problem 12-1A certain memory has a capacity of 16K × 32. How many words does it store? What is the number of bits per word? How many memory cells does it contain?
What is the function of the W̅E̅ input?
What is the benefit of address multiplexing?
List the advantages of dynamic RAM compared with static RAM.
Which memory technology generally uses the least power?
Why do some RAM chips have common input/output pins?
Describe how a computer uses a bootstrap program.
(a) A certain semiconductor memory chip is specified as 2K × 8. How many words can be stored on this chip? What is the word size? How many total bits can this chip store?(b) Which memory stores the most bits: a 5M × 8 memory or a memory that stores 1M words at a word size of 16 bits?
What is the principal reason for using a cache memory?
The MCM6209C is a 64K × 4 static-RAM chip. How many of these chips are needed to form a 1M × 4 module?
What is the main advantage of flash memory over EPROMs?
What is the most common magnetic storage device in use today?
True or false: An MROM can be programmed by the user.
Are SIMMs and DIMMs interchangeable?
What signal from a microcontroller would normally be connected to the OE input of a ROM?
True or false:(a) In most DRAMs, it is necessary to read only from one cell in each row in order to refresh all cells in that row.(b) In the burst refresh mode, the entire array is refreshed by one RAS pulse.
What input address code is required if we want to read the data from register 9 in Figure 12-7? CS OE A A A A ROW SELECT 0 1 2 3 1-of-4 decoder MSB E COLUMN SELECT 0 1-of-4 decoder 1 2 3 MSB E Row 0 Row 1 Row 2 Row 3 Column 0 Column 1 Column 2 Column 0 Register 0 Register 1 Register 2 Register 3
True or false: All ROMs are nonvolatile.
True or false:(a) During a read cycle, the R̅A̅S̅ signal is activated before the C̅A̅S̅ signal.(b) During a write operation, C̅A̅S̅ is activated before R̅A̅S̅.(c) WE is held LOW for the entire write operation.(d) The address inputs to a DRAM will change twice during a read or a write
Name the three groups of lines that connect the CPU and the internal memory.
How many address inputs, data inputs, and data outputs are required for a 16K × 12 memory?
Describe the array structure of a 64K × 1 DRAM.
A certain memory has a capacity of 16K × 32. How many words does it store? What is the number of bits per word? How many memory cells does it contain?
Define the following terms.(a) Memory cell(b) Memory word(c) Address(d) Byte(e) Access time
What are the main drawbacks of dynamic RAM compared with static?
How does a static-RAM cell differ from a dynamic-RAM cell?
Describe the input conditions needed to read a word from a specific RAM address location.
For the ADC0804 in Figure 11-21, determine:(a) The binary output produced with an analog input of 1.168 V.(b) The nominal analog input voltage that produces an output of 01100111.(c) The range of analog input values that will produce an output of 01100111.Figure 11-21 Analog 0.5-3.5 V N
An ADC0804 is to be used in an application that requires a resolution of 10 mV.(a) What voltage should we apply to the VREF/2 pin?(b) What analog input range can this circuit digitize?(c) What is the nominal full-scale input voltage?(d) What is the minimum input voltage that will produce a
Compare the maximum conversion times of a 10-bit digital-ramp ADC and a 10-bit successive-approximation ADC if both utilize a 500-kHz clock frequency.
An eight-bit SAC has a resolution of 20 mV. What will its digital output be for an analog input of 2.17 V?
What will happen to the operation of a digital-ramp ADC if the analog input VA is greater than the full-scale value?
A certain eight-bit ADC, similar to Figure 11-13, has a full-scale input of 2.55 V (i.e., VA = 2.55 V produces a digital output of 11111111). It has a specified error of ±1/4 LSB. Determine the maximum amount of error in the measurement.Figure 11-13
For the same ADC of Example 11-12, determine the approximate range of analog input voltages that will produce the same digital result of 01011101012 = 37310.Data from Example 11-12Assume the following values for the ADC of Figure 11-13: clock frequency = 1 MHz; VT = 0.1 mV; DAC has F.S. output =
Assume the following values for the ADC of Figure 11-13: clock frequency = 1 MHz; VT = 0.1 mV; DAC has F.S. output = 10.23 V and a 10-bit input. Determine the following values.(a) The digital equivalent obtained for VA = 3.728 V (b) The conversion time (c) The resolution of this converterFigure
How would the staircase waveform appear if the C input to the DAC of Figure 11-3 is open? Assume that the DAC inputs are TTL-compatible.Figure 11-3 Clock Four-bit counter D C B A D/A converter Resolution = 1 V OV VOUT Full scale (input = 1111) Resolution= Input recycled to 0000 step size = 1 V 15
A certain eight-bit DAC has a full-scale output of 2 mA and a full-scale error of ±0.5, F.S. What is the range of possible outputs for an input of 10000000?
Assume that VREF = 10 V for the DAC in Figure 11-8. What are the resolution and full-scale output of this converter?Figure 11-8 +VREF Bo (LSB) 5 2 R 2 R 2 R R R B1 B₂ 2 R R B3 (MSB) 2 R LOUT R www VOUT = -VREF 16 XB VOUT
Assume that VREF = 10 V and R = 10 kΩ. Determine the resolution and the full-scale output for this DAC. Assume that RL is much smaller than R.
What is the advantage of a smaller (finer) resolution?
(a) Determine the weight of each input bit of Figure 11-5(a).(b) Change RF to 250Ω and determine the full-scale output.Figure 11-5(a) 1 ΚΩ D W MSB 2 ΚΩ co B A 4 ΚΩ 8 ΚΩ LSB Digital inputs: 0 V or 5 V (a) RF = 1 k www Op- amp +Vs -Vs VOUT
True or false: The percentage resolution of a DAC depends only on the number of bits.
For the converter of Example 11-12, determine the digital output for VA = 1.345 V. Repeat for VA = 1.342 V.Data from Example 11-12Assume the following values for the ADC of Figure 11-13: clock frequency = 1 MHz; VT = 0.1 mV; DAC has F.S. output = 10.23 V and a 10-bit input. Determine the following
Using nine bits, how close to 326 rpm can the motor speed be adjusted?
For the system of Figure 11-4, how many bits should be used if the computer is to control the motor speed within 0.4 rpm?Figure 11-14 lOUT Current Bitty DAC 0-2 MA amp. Computer Motor 0-1000 rpm
Give one advantage and one disadvantage of a digital-ramp ADC.
Figure 11-4 shows a computer controlling the speed of a motor. The 0- to 2-mA analog current from the DAC is amplified to produce motor speeds from 0 to 1000 rpm (revolutions per minute). How many bits should be used if the computer is to be able to produce a motor speed that is within 2 rpm of the
What is the function of an actuator?
How many interpolated data points are inserted between samples when performing 4X oversampled digital filtering? How many for 8X oversampling?
How many output data bits does a sigma/delta modulator use?
What occurs if the signal is sampled at less than the minimum frequency determined in question 3?
How many different output voltages can a 12-bit DAC produce?
True or false: Everything else being equal, a 10-bit digital-ramp ADC will have a better resolution, but a longer conversion time, than an eight-bit ADC.
A 10-bit DAC has a step size of 10 mV. Determine the full-scale output voltage and the percentage resolution.
What function does a DAC perform?
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