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computer science
systems analysis and design 12th

Microelectronics Circuit Analysis And Design 4th Edition Donald A. Neamen - Solutions

Consider a three-input CMOS NAND logic circuit similar to the two-input circuit shown in Figure 16.34(a). Using a computer simulation, investigate the voltage transfer characteristics and switching characteristics for various NMOS and PMOS width-to-length ratios. What is the optimum relation
Using a computer simulation, investigate the \(Q\) and \(\bar{Q}\) values in the CMOS RAM cell shown in Figure 16.76 during read and write cycles for various transistor width-to-length ratios. In particular, consider the relations given by Equations (16.82) and (16.84).Figure 16.76:-Equation 16.82
Design a classic CMOS logic circuit that will implement the logic function \(Y=A \cdot(B+C)+D \cdot E\).
Design clocked CMOS logic circuits that will implement the logic functions (a) \(Y=[A \cdot B+C \cdot D]\) and (b) \(Y=[A \cdot(B+C)+D]\).
Design an NMOS pass logic network that implements the logic functions described in Problem 16.111.Data From Problem 16.111:-Design clocked CMOS logic circuits that will implement the logic functions (a) \(Y=[A \cdot B+C \cdot D]\) and (b) \(Y=[A \cdot(B+C)+D]\).
Design a clocked CMOS dynamic shift register in which the output becomes valid on the positive-going edge of a clock signal.
Describe the difference between an active filter and a passive filter. What is the primary advantage of an active filter?
Sketch the general characteristics of a low-pass filter, a high-pass filter, and a band-pass filter.
Consider a low-pass filter. What is the slope of the roll-off with frequency for a (a) one-pole filter, (b) two-pole filter, (c) three-pole filter, and (d) four-pole filter?
What characteristic defines a Butterworth filter?
Describe how a capacitor in conjunction with two switching transistors can behave as a resistor.
Sketch a one-pole low-pass switched-capacitor filter circuit.
Explain the two basic principles that must be satisfied in an oscillator circuit.
Describe and explain the operation of a phase-shift oscillator.
Describe and explain the operation of a Wien-bridge oscillator.
Sketch the circuit and characteristics of a basic inverting Schmitt trigger.
What is meant by bistable and astable circuits?
What is the primary advantage of a Schmitt trigger circuit.
Sketch the circuit and explain the operation of a Schmitt trigger oscillator.
Describe how an op-amp in conjunction with a class-AB output stage can be used as a power amplifier.
Sketch a bridge power amplifier and describe its operation.
Sketch the basic circuit block diagram of a voltage regulator and explain the principle of operation.
Define load regulation of a voltage regulator.
Sketch the basic circuit of a series-pass voltage regulator.
(a) Design a single-pole high-pass filter with a gain of 8 in the passband and a \(3 \mathrm{~dB}\) frequency of \(30 \mathrm{kHz}\). The maximum resistance is to be \(210 \mathrm{k} \Omega\).(b) Repeat part (a) for a gain of -20 in the passband and a \(3 \mathrm{~dB}\) frequency of \(20
Consider a Butterworth low-pass filter. Determine the reduction in gain (in \(\mathrm{dB}\) ) at \(f=1.5 f_{3 \mathrm{~dB}}\) for a (a) two-pole, (b) three-pole, (c) four-pole, and (d) five-pole filter.
The specification in a high-pass Butterworth filter design is that the voltage transfer function magnitude at \(f=0.9 f_{3 \mathrm{~dB}}\) is \(6 \mathrm{~dB}\) below the maximum value. Determine the required order of filter.
(a) Design a two-pole high-pass Butterworth active filter with a cutoff frequency at \(f_{3 \mathrm{~dB}}=25 \mathrm{kHz}\) and a unity gain magnitude at high frequency. (b) Determine the magnitude (in \(\mathrm{dB}\) ) of the gain at (i) \(f=22 \mathrm{kHz}\), (ii) \(f=25 \mathrm{kHz}\), and (iii)
(a) Design a three-pole low-pass Butterworth active filter with a cutoff frequency at \(f_{3 \mathrm{~dB}}=20 \mathrm{kHz}\) and a unity gain magnitude at low frequency. (b) Determine the magnitude (in \(\mathrm{dB}\) ) of the gain at (i) \(f=10 \mathrm{kHz}\), (ii) \(f=15 \mathrm{kHz}\), (iii)
Starting with the general transfer function given by Equation (15.7), derive the relationship between \(R_{1}\) and \(R_{2}\) in the two-pole high-pass Butterworth active filter.Equation 15.7:- T(s) = = V(s) Vi(s) YY2 YY2+Y4(Y1Y2+Y3)
A low-pass Butterworth filter is to be designed such that the magnitude of the voltage transfer function at \(f=1.2 f_{3 \mathrm{~dB}}\) is \(14 \mathrm{~dB}\) below the maximum gain value. Determine the required order of filter.
A high-pass Butterworth filter is to be designed with a cutoff frequency of \(f_{3 \mathrm{~dB}}=4 \mathrm{kHz}\). The gain magnitude is to be reduced by \(12 \mathrm{~dB}\) at \(f=3 \mathrm{kHz}\) from the maximum gain value. Determine the required order of filter.
A low-pass filter is to be designed to pass frequencies in the 0 to \(12 \mathrm{kHz}\) range. The gain of the amplifier is to be +10 at the low frequency and change by no more than 10 percent over the frequency range. In addition, the gain of the amplifier for frequencies greater than \(14
Consider a high-pass Butterworth filter. Determine the ratio of the gain magnitude (in \(\mathrm{dB}\) ) of the filter at a frequency \(f=0.8 f_{3 \mathrm{~dB}}\) compared to the high-frequency value for a (a) three-pole, (b) five-pole, and (c) seven-pole filter.
Consider a low-pass Butterworth filter. Determine the ratio of the gain magnitude (in \(\mathrm{dB}\) ) of the filter at a frequency \(f=1.4 f_{3 \mathrm{~dB}}\) compared to the lowfrequency value for a (a) three-pole, (b) five-pole, and (c) seven-pole filter.
Design a special type of first-order filter (one capacitor) in which the gain magnitude is 25 for frequencies less than approximately \(25 \mathrm{kHz}\) and is 1 for frequencies greater than approximately \(25 \mathrm{kHz}\).
An amplitude-modulated radio signal consists of an \(80 \mathrm{~Hz}\) to \(12 \mathrm{kHz}\) audio signal superimposed on a \(770 \mathrm{kHz}\) carrier signal. A low-pass filter is to be designed in which the gain in the passband is unity and the carrier signal is attenuated by at least \(-100
A band-reject filter may be designed by combining a low-pass filter and a high-pass filter with a summing amplifier. A \(60 \mathrm{~Hz}\) signal is to be at least \(-50 \mathrm{~dB}\) below the maximum gain value of \(0 \mathrm{~dB}\) with a two-pole low-pass Butterworth filter and a two-pole
Consider the bandpass filter in Figure P15.15. (a) Show that the voltage transfer function is\[A_{v}(s)=\frac{v_{O}}{v_{I}}=\frac{-1 / R_{4}}{\left(1 / R_{1}\right)+s C+1 /\left(s C R_{2} R_{3}\right)}\](b) For \(C=0.1 \mu \mathrm{F}, R_{1}=85 \mathrm{k} \Omega, R_{2}=R_{3}=300 \Omega, R_{4}=3
Consider the circuit in Figure P15.16. (a) Derive the expressions for the magnitude and phase of the voltage transfer function. (b) Plot the phase versus frequency for \(R=10 \mathrm{k} \Omega\) and \(C=15.9 \mathrm{nF}\). [Note: this filter is referred to as an all-pass filter in that the
For each of the circuits in Figures P15.17, derive the expressions for the voltage transfer function \(T(s)=V_{o}(s) / V_{i}(s)\) and the cutoff frequency \(f_{3 \mathrm{~dB}}\). R www Figure P15.17 (a) R ww C C R R ww (b) +
The circuit in Figure P15.18 is a bandpass filter. (a) Derive the expression for the voltage transfer function \(T(s)\). (b) If \(R_{1}=10 \mathrm{k} \Omega\), determine \(R_{2}, C_{1}\), and \(C_{2}\) such that the magnitude of the midband gain is 50 and the cutoff frequencies are \(200
A simple bandpass filter can be designed by cascading one-pole high-pass and one-pole low-pass filters. Using op-amp circuits similar to those in Figure 15.3, design a bandpass filter with cutoff frequencies of \(150 \mathrm{~Hz}\) and \(20 \mathrm{kHz}\) and with a midband gain of \(30
The clock frequency in the switched-capacitor circuit in Figure 15.12 (a) is \(f_{C}=50 \mathrm{kHz}\). Find the equivalent resistance that is simulated when(a) \(C=0.5 \mathrm{pF}\),(b) \(C=2 \mathrm{pF}\), and(c) \(C=10 \mathrm{pF}\).Figure 15.12(a):- Vo- M I (a) 02 M2 -0 V2
In the switched-capacitor circuit in Figure 15.12(a), the voltages are \(V_{1}=2 \mathrm{~V}\) and \(V_{2}=1 \mathrm{~V}\), the capacitor value is \(C=10 \mathrm{pF}\), and the clock frequency is \(f_{C}=100 \mathrm{kHz}\). (a) Determine the charge transferred from \(V_{1}\) to \(V_{2}\) during
Consider the switched-capacitor filter in Figure 15.13(b). Design the circuit for a low-frequency gain of -10 and a cutoff frequency of \(10 \mathrm{kHz}\). The clock frequency must be 10 times the cutoff frequency and the largest capacitance is to be \(30 \mathrm{pF}\). Find the required values of
The circuit in Figure P15.23 is a switched-capacitor integrator. Let \(C_{F}=\) \(30 \mathrm{pF}\) and \(C_{1}=5 \mathrm{pF}\), and assume the clock frequency is \(100 \mathrm{kHz}\). Also, let \(v_{I}=1 \mathrm{~V}\).(a) Determine the integrating \(R C\) time constant.(b) Find the change in output
Consider the phase shift oscillator in Figure 15.15. (a) For \(R=20 \mathrm{k} \Omega\) and \(C=0.001 \mu \mathrm{F}\), determine the frequency of oscillation. What is the required value of \(R_{2}\) ? (b) Design the circuit such that the frequency of oscillation is \(f_{o}=25 \mathrm{kHz}\). Let
In the phase-shift oscillator in Figure 15.15, the capacitor at the noninverting terminal of op-amp \(A_{1}\) is replaced by a variable capacitor \(C_{V}\). (a) Derive the expression for the frequency of oscillation. (b) If \(C=10 \mathrm{pF}, R=10 \mathrm{k} \Omega\), and \(C_{V}\) is variable
Consider the phase shift oscillator in Figure 15.16. (a) Determine the frequency of oscillation for \(R=12 \mathrm{k} \Omega\) and \(C=150 \mathrm{pF}\). What is the required value of \(R_{2}\) ? (b) Design the circuit such that the frequency of oscillation is \(f_{o}=22 \mathrm{kHz}\). Let
Analyze the phase-shift oscillator in Figure 15.16. Show that the frequency of oscillation is given by Equation (15.46) and that the condition for oscillation is given by Equation (15.47). C C C R ww www R R R ww Figure 15.16 Phase-shift oscillator circuit
The circuit in Figure P15.28 is an alternative configuration of a phaseshift oscillator. (a) Assume that \(R_{1}=R_{2}=R_{3}=R_{A_{1}}=R_{A_{2}}=R_{A_{3}} \equiv R\) and \(C_{1}=C_{2}=C_{3} \equiv C\). Show that the frequency of oscillation is \(\omega_{o}=\sqrt{3} / R C\). (b) Assume equal
In the circuit in Figure P15.28, let \(R_{F 1}=R_{F 2}=R_{F 3} \equiv R_{F}\), \(R_{2}=R_{3}=R_{A 1}=R_{A 2}=R_{A 3} \equiv R, C_{1}=C_{2}=C_{3} \equiv C\), and let \(R_{1}\) be a variable resistance \(R_{1}=R_{V}\). (a) Derive the expression for the frequency of oscillation. (b) If \(R_{V}=R\),
Consider the phase-shift oscillator in Figure P15.30. (a) Derive the expression for the frequency of oscillation. (b) Determine the condition for oscillation. (c) For \(R=20 \mathrm{k} \Omega\), find \(C\) and \(R_{F}\) that will produce sustained oscillations at \(f_{o}=22 \mathrm{kHz}\). R www R
Consider the phase-shift oscillator in Figure P15.30. (a) Assume the first resistor that is connected to \(v_{o}\) is a variable resistor \(R_{V}\). Derive the expression for the frequency of oscillation in terms of \(C, R\), and \(R_{V}\). (b) Using the results of part (a), determine the range in
A Wien-bridge oscillator is shown in Figure P15.32. (a) Derive the expression for the frequency of oscillation. (b) What is the condition for sustained oscillations? R www ICB RB CA ___ Figure P15.32 R ww RA Oa o-
Consider the oscillator circuit in Figure P15.33. (a) Derive the expression for the loop gain \(T(s)\). (b) Determine the expression for the frequency of oscillation. (c) Find the condition for oscillation. R R ww R L_ Figure P15.33 R + -0% L
Design the Wein-bridge oscillator in Figure 15.17 to oscillate at \(f_{o}=35 \mathrm{kHz}\). Choose appropriate component values. (up) 0- R ww Vx R ww Vyr + IC R IZ R Zp Figure 15.17 Wien-bridge oscillator
The Colpitts oscillator in Figure 15.19 is biased at \(I_{D}=0.8 \mathrm{~mA}\). The transistor parameters are \(V_{T N}=0.8 \mathrm{~V}\) and \(K_{n}=0.7 \mathrm{~mA} / \mathrm{V}^{2}\). Let \(C_{1}=0.02 \mu \mathrm{F}\) and \(R=2 \mathrm{k} \Omega\). Design the circuit to oscillate at \(f_{o}=350
Figure P15.36 shows a Colpitts oscillator with a BJT. Assume \(r_{\pi}\) and \(r_{o}\) are both very large. Derive the expressions for the frequency of oscillation and the condition of oscillation. V+ L C C- C 8 HH C: V- Figure P15.36 OVO RI.
Consider the ac equivalent circuit of the Hartley oscillator in Figure 15.21. (a) Derive the expression for the frequency of oscillation. (b) Determine the condition for sustained oscillations. ww R L2 Figure 15.21 C HH L
For the Hartley oscillator in Figure 15.21, assume \(r_{\pi} \rightarrow \infty\) and let \(g_{m}=30 \mathrm{~mA} /\) V. (a) Derive the expression for the frequency of oscillation. (b) Show that the condition for oscillation is given by \(g_{m} R=L_{1} / L_{2}\). (c) Design the circuit to oscillate
Find the loop gain functions \(T(s)\) and \(T(j \omega)\), the frequency of oscillation, and the \(R_{2} / R_{1}\) required for oscillation for the circuit in Figure P15.39. R R www ww C www R Figure P15.39
Repeat Problem 15.39 for the circuit in Figure P15.40.Data From Problem 15.39:-Find the loop gain functions \(T(s)\) and \(T(j \omega)\), the frequency of oscillation, and the \(R_{2} / R_{1}\) required for oscillation for the circuit in Figure P15.39. R R www ww C www R Figure P15.39
Repeat Problem 15.39 for the circuit in Figure P15.41.Data From Problem 15.39:-Find the loop gain functions \(T(s)\) and \(T(j \omega)\), the frequency of oscillation, and the \(R_{2} / R_{1}\) required for oscillation for the circuit in Figure P15.39. R R www ww R Figure P15.41 www R L
For the comparator in the circuit in Figure 15.26(a), the output saturation voltages are \(\pm 9 \mathrm{~V}\). Let \(V_{\text {REF }}=5 \mathrm{~V}\). Let \(R_{2}\) be a fixed resistor in series with a potentiometer. Design the circuit such that the crossover voltage can easily be varied over the
Consider the Schmitt trigger shown in Figure 15.29(a). Assume the saturated output voltages are \(V_{H}=+10 \mathrm{~V}\) and \(V_{L}=-10 \mathrm{~V}\). The range of the input voltage is \(-5 \leq v_{I} \leq 5 \mathrm{~V}\). Design the circuit such that the hysteresis width is \(0.4 \mathrm{~V}\)
The saturated output voltages of the Schmitt trigger in Figure 15.28 (a) are \(V_{H}=+9 \mathrm{~V}\) and \(V_{L}=-9 \mathrm{~V}\). The range of the input voltage is \(-9 \leq v_{I} \leq 9 \mathrm{~V}\).(a) Design the circuit whose minimum resistance is \(2 \mathrm{k} \Omega\) and such that the
A Schmitt trigger circuit is shown in Figure 15.28(a). The parameters are \(V_{H}=+10 \mathrm{~V}, V_{L}=-10 \mathrm{~V}, R_{1}=2 \mathrm{k} \Omega\), and \(R_{2}=48 \mathrm{k} \Omega\). (a) Determine the crossover voltages \(V_{T H}\) and \(V_{T L}\). (b) Assume a sinusoidal voltage \(v_{I}=10
Consider the Schmitt trigger in Figure P15.46. Assume the saturated output voltages are \(\pm V_{P}\). (a) Derive the expression for the crossover voltages \(V_{T H}\) and \(V_{T L}\). (b) Let \(R_{A}=10 \mathrm{k} \Omega, R_{B}=20 \mathrm{k} \Omega, R_{1}=5 \mathrm{k} \Omega, R_{2}=20 \mathrm{k}
The saturated output voltages are \(\pm V_{P}\) for the Schmitt trigger in Figure P15.47. (a) Derive the expressions for the crossover voltages \(V_{T H}\) and \(V_{T L}\) (b) If \(V_{P}=12 \mathrm{~V}, V_{\mathrm{REF}}=-10 \mathrm{~V}\), and \(R_{3}=10 \mathrm{k} \Omega\), find \(R_{1}\) and
(a) Plot the voltage transfer characteristics of the comparator circuit in Figure P15.48 assuming the open-loop gain is infinite. Let the reverse Zener voltage be \(V_{Z}=5.6 \mathrm{~V}\) and the forward diode voltage be \(V_{\gamma}=0.6 \mathrm{~V}\).(b) Repeat part (a) for an open-loop gain of
Consider the Schmitt trigger in Figure 15.30(a). (a) Derive the expression for the switching point and crossover voltages as given in Equations (15.76) and (15.77). (b) Let \(V_{H}=+12 \mathrm{~V}\) and \(V_{L}=-12 \mathrm{~V}\). The minimum resistance is to be \(4 \mathrm{k} \Omega\). Determine
Consider the Schmitt trigger in Figure 15.31(a). (a) Derive the expressions for the switching point and crossover voltages, as given in Equations (15.78) and (15.79). (b) Let \(V_{H}=12 \mathrm{~V}, V_{L}=-12 \mathrm{~V}\), and \(R_{2}=20 \mathrm{k} \Omega\). Determine \(R_{1}\) and
Consider the Schmitt trigger in Figure P15.51. The saturated output voltages of the op-amp are \(V_{H}=+10 \mathrm{~V}\) and \(V_{L}=-10 \mathrm{~V}\). Assume the diode turn-on voltage is \(0.7 \mathrm{~V}\). The range of the input voltage is \(-2 \leq v_{I} \leq+2 \mathrm{~V}\). (a) Determine the
The saturated output voltages of the comparator in the circuit shown in Figure 15.33 are \(\pm 10 \mathrm{~V}\). Assume forward diode voltages of \(0.7 \mathrm{~V}\) and reverse Zener voltages of \(5.6 \mathrm{~V}\). The range of the input voltage is \(-2 \leq v_{I} \leq+2 \mathrm{~V}\). (a) Find
Consider the Schmitt trigger with limiter, as shown in Figure 15.34. Assume the forward diode turn-on voltage \(V_{\gamma}\) is \(0.7 \mathrm{~V}\). (a) Determine \(V_{\text {REF }}\) such that the bistable output voltages at \(v_{I}=0\) are \(\pm 5 \mathrm{~V}\). (b) Find values of \(R_{1}\) and
Consider the inverting Schmitt trigger with limiting network, as shown in Figure 15.34(a). Show that the crossover voltages are those given in Figure 15.34(b). VREF 100 ww ww R D D2 1 1 1 ww 1 vo (VREF + 2Vy) VTH R R+ R R VTL =- (VREF+ +2V) R+R -VREF R -(VREF+2Vy) ww (b) (a) Figure 15.34 (a)
(a) For the Schmitt trigger with limiter in Figure P15.55(a), find the two output voltage values at \(v_{I}=0\) and the two crossover voltages. (b) Derive the expression for the slope of \(v_{O}\) versus \(v_{I}\) for \(v_{I}>V_{T H}\). VREF 1 R Figure P15.55 (a) -VREF R ww
Consider the Schmitt trigger oscillator in Figure 15.35. The circuit parameters are \(R_{1}=10 \mathrm{k} \Omega, R_{2}=20 \mathrm{k} \Omega, R_{X}=40 \mathrm{k} \Omega\), and \(C_{X}=0.02 \mu \mathrm{F}\). The saturated output voltages are \(\pm 5 \mathrm{~V}\). (a) Write the expressions for
Repeat Problem 15.56 for saturated output voltages of \(V_{H}=+5 \mathrm{~V}\) and \(V_{L}=-10 \mathrm{~V}\).Data From Problem 15.56:-Consider the Schmitt trigger oscillator in Figure 15.35. The circuit parameters are \(R_{1}=10 \mathrm{k} \Omega, R_{2}=20 \mathrm{k} \Omega, R_{X}=40 \mathrm{k}
Design the Schmitt trigger circuit in Figure 15.35 to produce a square-wave output signal at a frequency of \(f_{o}=12 \mathrm{kHz}\) and a 50 percent duty cycle. Choose standard component values. Cx: C Rx www Figure 15.35 R
Consider the circuit in Figure P15.59. The saturated output voltages of the Schmitt trigger comparator are \(\pm 10 \mathrm{~V}\). Assume that at \(t=0\), output \(v_{o 1}\) switches from its low state to its high state and \(C_{Y}\) is uncharged. Plot \(v_{o 1}\) and \(v_{o}\) versus time over two
The saturated output voltages of the comparator in Figure P15.60 are \(\pm 10 \mathrm{~V}\). (a) Find \(R_{x}\) such that the frequency of oscillation is \(500 \mathrm{~Hz}\) when the potentiometer is connected to point A. (b) Using the results of part (a), determine the oscillator frequency when
(a) The monostable multivibrator in Figure 15.37 is to be designed to produce a \(250 \mu\) s output pulse. Assume saturated output voltages of \(\pm 10 \mathrm{~V}\), and let \(V_{\gamma}=0.7 \mathrm{~V}, R_{1}=20 \mathrm{k} \Omega\), and \(R_{2}=12 \mathrm{k} \Omega\). (b) Determine the minimum
A monostable multivibrator is shown in Figure 15.37. The parameters are \(R_{X}=20 \mathrm{k} \Omega, C_{X}=1.2 \mu \mathrm{F}\), and \(R_{1}=R_{2}=20 \mathrm{k} \Omega\). The saturated output voltages are \(\pm 5 \mathrm{~V}\). (a) What is the output voltage pulse width? (b) Determine the recovery
Figure 15.40 shows the 555 timer connected in the monostable multivibrator mode. (a) Design the circuit to provide an output pulse 60 seconds wide. (b) Determine the recovery time. RA +VCC Reset +VCC C + vc(t) Discharge Threshold Vin + I Trigger Ground Figure 15.40 555 Output vo
Design a 555 monostable multivibrator to provide a \(5 \mu \mathrm{s}\) pulse. What is the recovery time?
A 555 timer is connected in the astable mode as shown in Figure 15.41. Design the circuit such that the frequency of oscillation is \(f_{o}=80 \mathrm{kHz}\) and the duty cycle is 60 percent. Let \(R_{A}=25 \mathrm{k} \Omega\). +Vcc RA +Vcc Reset Discharge ww RB 555 Output Threshold Trigger +
A 555 ICC is connected as shown in Figure P15.66. Determine the range of oscillation frequency and the duty cycle. R = 10 v+= 10 V 8 4 R = 7 10 2 3 R3 = 100 6 51 C = 0.01 F 0.01 Figure P15.66
Repeat Problem 15.66 for the circuit in Figure P15.67.Data From Problem 15.66:-A 555 ICC is connected as shown in Figure P15.66. Determine the range of oscillation frequency and the duty cycle. R = R3 = 50 R = www ww V+ 10 V 8 4 7 2 3 6 C= 0.01 0.01 F Figure P15.67 5 1
The LM380 power amplifier in Figure 15.42 is biased at \(V^{+}=22 \mathrm{~V}\). Let \(\beta_{n}=100\) and \(\beta_{p}=20\) for the npn and pnp transistors, respectively. (a) Determine the quiescent collector currents in transistors \(Q_{1}\) through \(Q_{6}\). (b) Assume that diodes \(D_{1}\) and
An LM380 must deliver ac power to a \(10 \Omega\) load. The maximum power dissipated in the amplifier must be limited to \(2 \mathrm{~W}\) and the maximum allowed distortion must be limited to 3 percent. Determine: (a) the maximum power that can be delivered to the load, (b) the maximum supply
(a) Design the bridge circuit in Figure 15.46 such that the gain magnitude of each op-amp circuit is 12. (b) A load resistance of \(R_{L}=12 \Omega\) that is to dissipate an average power of \(\widehat{P_{L}}=15 \mathrm{~W}\) is connected to the output. Determine the peak output voltage at each
Another form of the bridge power amplifier is shown in Figure P15.71. This amplifier has a very high input resistance since the input is to the noninverting terminal of an op-amp. (a) Derive the expression for the voltage gain \(A_{v}=v_{L} / v_{I}\). (b) Design the circuit to provide a gain of
Figure P15.72 shows an audio amplifier using two identical op-amps connected in a bridge configuration. (a) Derive the expression for the voltage gain \(A_{v}=v_{L} / v_{I}\). (b) Design the system such that \(\left|v_{O 1}\right|=\left|v_{O 2}\right|=12 v_{I}\). The largest resistor value is to be
(a) Design the circuit shown in Figure P15.72 such that \(v_{O 1}=-v_{O 2}\) and the voltage gain \(A_{v}=v_{L} / v_{I}=25\). The largest resistor value is to be limited to \(100 \mathrm{k} \Omega\). (b) If the peak value of each op-amp output voltage is limited to \(\pm 12 \mathrm{~V}\) and the
Transistors \(Q_{1}\) and \(Q_{2}\) in the voltage regulator circuit in Figure P15.74 have parameters \(\beta=200, V_{E B}(\) on \()=0.7 \mathrm{~V}\), and \(V_{A}=100 \mathrm{~V}\). The zero-current Zener voltage is \(V_{Z O}=6.3 \mathrm{~V}\) and the Zener resistance is \(r_{z}=15 \Omega\).
(a) The output voltage of a voltage regulator decreases by \(8 \mathrm{mV}\) as the load current changes from 0 to \(2 \mathrm{~A}\). If the output voltage changes linearly with load current, determine the output resistance of the regulator. (b) If the output resistance of a voltage regulator is
Consider the three-terminal voltage regulator in Figure 15.51, with parameters as given in Example 15.16. If the maximum load current is \(I_{O}(\max )=100 \mathrm{~mA}\), determine the minimum applied power supply voltage \(V^{+}\)that will still maintain all transistors biased in the active

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