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introduction java program

Fundamentals Of Digital Logic With Verilog Design 3rd Edition Stephen Brown, Zvonko Vranesic - Solutions

Consider the circuit in Figure P11.3. Sensitize each path in this circuit to obtain a complete test set that comprises a minimum number of tests. W1 W2 W3 W4 D D W5 D
For the circuit of Figure 11.4a, show the tests that can detect each of the faults: w1/0, w4/1, g/0, and c/1. W1 W2 W3 WA D b on 8 (a) Circuit D h k
Suppose that the tests w1w2w3w4 = 0100, 1010, 0011, 1111, and 0110 are chosen randomly to test the circuit in Figure 11.3. What percentage of single faults are detected using these tests? WI W2 W3 ▼ b D W4 d с f
Consider the circuit in Figure P11.4. Are all single stuck-at-0 and stuck-at-1 faults in this circuit detectable? If not, explain why. W₁ W2 W3 D D f
The circuit in Figure P11.5 determines the parity of a four-bit data unit. Derive a minimal test set that can detect all single stuck-at-0 and stuck-at-1 faults in this circuit. Would your test set work if the XOR gates are implemented using the circuit in Figure 8.9c? Can your result be extended
In Section 8.4.2 we showed how the ∗-product operation can be used to find the prime implicants of a given function f . Another possibility is to find the prime implicants by expanding the implicants in the initial cover of the function. An implicant is expanded by removing one literal to create
In Section 7.1 we showed a digital system with three registers, R1 to R3, and we designed a control circuit that can be used to swap the contents of registers R1 and R2. Give an ASM chart that represents this digital system and the swap operation.Data From Section 7.1Outputs of two ordinary logic
(a) For the ASM chart derived in Problem 7.1, show another ASM chart that specifies the required control signals to control the datapath circuit. Assume that multiplexers are used to implement the bus that connects the registers, as shown in Figure 7.4.(b)Write complete Verilog code for the system
In Section 7.2 we designed a processor that performs the operations listed in Table 7.1. Design a modified circuit that performs an additional operation Swap Rx, Ry. This operation swaps the contents of registers Rx and Ry. Use three bits f2 f1 f0 to represent the input F shown in Figure 7.11
In Section 7.2 we gave the design for a circuit that works as a processor. Give an ASM chart that describes the functionality of this processor.Data From Section 7.2A second example of a digital system like the one in Figure 7.2 is shown in Figure 7.9. It has four n-bit registers, R0, . . . ,
The ASM chart in Figure 7.17, which describes the bit-counting circuit, includes Moore-type outputs in states S1, S2, and S3, and it has a Mealy-type output in state S2.(a) Show how the ASM chart can be modified such that it has only Moore-type outputs in state S2.(b) Give the ASM chart for the
(a) For the ASM chart derived in Problem 7.4, show another ASM chart that specifies the required control signals to control the data path circuit in the processor. Assume that multiplexers are used to implement the bus that connects the registers, R0 to R3, in the processor.(b) Write complete
Figure 7.24 shows the data path circuit for the shift-and-add multiplier. It uses a shift register for B so that b0 can be used to decide whether or not A should be added to P. A different approach is to use a normal register to hold operand B and to use a counter and multiplexer to select bit bi
Section 7.5 shows how to implement the traditional long division that is done by “hand.” A different approach for implementing integer division is to perform repeated subtraction as indicated in the pseudo-code in Figure P7.1.(a) Give an ASM chart that represents the pseudo-code in Figure
Write Verilog code for the divider circuit that has the data path in Figure 7.30 and the control circuit represented by the ASM chart in Figure 7.31. Clock Rsel- LR L ER E 0 EQ 0 Left-shift register n n E W an-1 Left-shift register n LA L EA
In the ASM chart in Figure 7.39, the two states S3 and S4 are used to compute the mean M = Sum/k. Show a modified ASM chart that combines states S3 and S4 into a single state, called S3. EC S1 S2 S3 S4 Reset LC, Ssel = 0, ES Ssel = 1, ES N LA, EB Div N ZZ S5 0 S Div, Done 1
Write Verilog code for the FSM represented by your ASM chart defined in Problem 7.10.Data From Problem 7.10In the ASM chart in Figure 7.39, the two states S3 and S4 are used to compute the mean M = Sum/k. Show a modified ASM chart that combines states S3 and S4 into a single state, called S3.
In the ASM chart in Figure 7.41, we specify the assignment Cj ← Ci in state S2, and then in state S3 we increment Cj by 1. Is it possible to eliminate state S3 if the assignment Cj ← Ci + 1 is performed in S2? Explain any implications that this change has on the control and datapath circuits.
Figure 7.40 gives pseudo-code for the sorting operation in which the registers being sorted are indexed using variables i and j. In the ASM chart in Figure 7.41, variables i and j are implemented using the counters Ci and Cj . A different approach is to implement i and j using two shift
The circuit designed in Section 7.6 uses an adder to compute the sum of the contents of the registers. The divider sub circuit used to compute M = Sum/k also includes an adder. Show how the circuit can be redesigned so that it contains only a single adder sub circuit that is used both for the
Design a circuit that finds the log2 of an operand that is stored in an n-bit register. Show all steps in the design process and state any assumptions made. Give Verilog code that describes your circuit.
Give Verilog code for the circuit designed in Problem 7.15, including both the data path and control circuits.Data From Problem 7.15The circuit designed in Section 7.6 uses an adder to compute the sum of the contents of the registers. The divider sub circuit used to compute M = Sum/k also includes
The pseudo-code for the sorting operation given in Figure 7.40 uses registers A and B to hold the contents of the registers being sorted. Show pseudo-code for the sorting operation that uses only register A to hold temporary data during the sorting operation. Give a corresponding ASM chart that
Give Verilog code for the sorting circuit designed in Problem 7.17.Data From Problem 7.17The pseudo-code for the sorting operation given in Figure 7.40 uses registers A and B to hold the contents of the registers being sorted. Show pseudo-code for the sorting operation that uses only register A to
Consider the design of a circuit that controls the traffic lights at the intersection of two roads. The circuit generates the outputs G1, Y 1, R1 and G2, Y 2, R2. These outputs represent the states of the green, yellow, and red lights, respectively, on each road. A light is turned on if the
Clock signals can be generated using special purpose chips. One example of such a chip is the 555 programmable timer, which is depicted in Figure P7.2. By choosing particular values for the resistors Ra and Rb and the capacitor C1, the 555 timer can be used to produce Clock (output) 4 2 1 5
Assume that you need to use a single-pole single-throw switch as shown in Figure 7.51a. Show how a counter can be used as a means of de bouncing the Data signal produced by the switch. VDD R www Li X Data (a) Single-pole single-throw switch
Implement the logic circuit in Figure 8.6b using NAND gates only. -f D Tx 8 Ix X4 먀 Ex
Implement the logic circuit in Figure 8.6b using NOR gates only. f D Tx 8 Ix X4 먀 Ex
Consider the function Derive a minimum-cost circuit that implements this function using NOT, AND, and OR gates. f = X3 X5 + X₁ X₂ X₁ + X ₁ X ₂ X 4 + X₁ X3 X₁ + X₁ X3 X₁ + X1 X2 X5 + X₁ X2X5.
In Figure 8.8 we decomposed the function f by first identifying sub functions in the rows of the Karnaugh map. Repeat this decomposition by first identifying sub functions in the columns of the Karnaugh map. x1x₂ X3 X4 00 01 11 10 00 01 11 10 1 1 XI x2 X5 X4 1 1 1 1 X5 = 0 1 g X3
Derive a minimum-cost circuit that implements the function f (x1, . . . , x4) = Σm(4, 7, 8, 11) + D(12, 15).
Create a BDD for the function in Figure 8.6 using the input order x1, x2, x3, x4. ²x¹x X3 X4 00 01 11 10 00 011 0 01 001 11 0 (1 10 00 (11) 1 1 0 (a) Product terms X₂1314 -X₁ X3 X4 X₂ X3 X4 -X₁ X3 X4 g X₂ (b) Multilevel circuit f
Repeat Problem 8.12 using the input order x4, x3, x2, x1.Data From Problem 8.12Create a BDD for the function in Figure 8.6 using the input order x1, x2, x3, x4. ²x¹x X3 X4 00 01 11 10 00 011 0 01 001 11 0 (1 10 00 (11) 1 1 0 (a) Product terms X₂1314 -X₁ X3 X4 X₂ X3 X4 X₁ X3 X4 g X₂ (b)
In Figure 8.7 we decomposed the function f by first identifying sub functions in the columns of the Karnaugh map. Repeat this decomposition by first identifying sub functions in the rows of the Karnaugh map. x1x2 X3 X4 00 0 01 + + 1 00 01 11 10 1 1 0 10 0 11 0 100 0 0 1 0 1 1 1 1 0 1 (a)
Create a BDD for the function in Figure 8.8 using the input order x1, x2, x3, x4, x5. x1x₂ X3 X4 00 01 11 10 00 01 11 10 1 1 XI x2 X5 X4 11 1 X5 = 0 1 1 g X3 X4 k X1 X₂ 00 01 11 10 00 01 11 10 1 (a) Karnaugh map for the function f 1 1 X5 = 1 (b) Circuit obtained using decomposition 1
Repeat Problem 8.14 using the input order x5, x4, x3, x2, x1.Data From Problem 8.14Create a BDD for the function in Figure 8.8 using the input order x1, x2, x3, x4, x5. x1x₂ X3 X4 00 01 11 10 00 01 11 10 1 1 XI x2 X5 X4 11 1 X5 = 0 1 1 g X3 X4 k X1 X₂ 00 01 11 10 00 01 11 10 1 (a) Karnaugh map
Find the simplest realization of the function f (x1, . . . , x4) = Σm(0, 3, 4, 7, 9, 10, 13, 14), assuming that the logic gates have a maximum fan-in of two.
Find the minimum-cost circuit for the function f (x1, . . . , x4) = m(0, 4, 8, 13, 14, 15). Assume that the input variables are available in uncomplemented form only.
For the function f = x1x3 + x2x4 in Example 8.21 show how to use Shannon’s expansion to derive the BDD in Figure 8.37b. 0 N 0 1 0 X1 E₁ 0 0 1 E₂ x2 X4 0 1 X3 (a) Reordered tree 1 0 x2 1 x2 0 0 0 1 X1 XA 1 0 X3 1 1 (b) Order X₁, X3, X2, X4
Use functional decomposition to find the best implementation of the function f (x1, . . . , x5) = m(1, 2, 7, 9, 10, 18, 19, 25, 31) + D(0, 15, 20, 26). How does your implementation compare with the lowest-cost SOP implementation? Give the costs.
Show how to swap the variables x2 and x3 in the BDD in Figure 8.37b to derive the BDD in Figure 8.35.Figure 8.35:Figure 8.37b: 0 X2 0 1 0 ХА X1 0 1 X3 1 1 X2 0 0 3 1
Use the tabular method discussed in Section 8.4.1 to find a minimum cost SOP realization for the functionData From Section 8.4.1A Tabular Method for MinimizationA tabular approach for minimization was proposed in the 1950s by Willard Quine [5] and Edward McCluskey [6]. It became popular under the
Show that the following distributive-like rules are valid (AB)#C= (A#C) - (B#C) (A + B)#C = (A#C) + (B#C)
Repeat Problem 8.18 for the functionData From Problem 8.18Use the tabular method discussed in Section 8.4.1 to find a minimum cost SOP realization for the functionData From Section 8.4.1A Tabular Method for MinimizationA tabular approach for minimization was proposed in the 1950s by Willard Quine
Repeat Problem 8.18 for the functionData From Problem 8.18Use the tabular method discussed in Section 8.4.1 to find a minimum cost SOP realization for the functionData From Section 8.4.1A Tabular Method for MinimizationA tabular approach for minimization was proposed in the 1950s by Willard Quine
Use the cubical representation and the method discussed in Section 8.4.2 to find a minimum cost SOP realization of the function f (x1, . . . , x4) = Σm(0, 2, 4, 5, 7, 8, 9, 15).Section 8.4.2Assume that the initial specification of a function f is given in terms of implicants that are not
Repeat Problem 8.22 for the functionData From Problem 8.22Use the cubical representation and the method discussed in Section 8.4.2 to find a minimum cost SOP realization of the function f (x1, . . . , x4) = Σm(0, 2, 4, 5, 7, 8, 9, 15).Section 8.4.2Assume that the initial specification of a
Use the cubical representation and the method discussed in Section 8.4.2 to find a minimum cost SOP realization of the function f (x1, . . . , x4) defined by the ON-set ON = {00x0, 100x, x010, 1111} and the don’t-care set DC = {00x1, 011x}.Section 8.4.2Assume that the initial specification of a
Repeat Problem 8.25 for the function in Example 8.15. Expand the implicants given in the initial cover C0.Data From Problem 8.25In Section 8.4.2 we showed how the ∗-product operation can be used to find the prime implicants of a given function f. Another possibility is to find the prime
Repeat Problem 8.27 for the function f (x1, . . . , x4) = Σm(2, 3, 6, 8, 9, 12).Data From Problem 8.27Find the minimum-cost circuit consisting only of two-input NAND gates for the function f (x1, . . . , x4) = Σm(0, 1, 2, 3, 4, 6, 8, 9, 12). Assume that the input variables are available in both
Find the minimum-cost circuit consisting only of two-input NOR gates for the function f (x1, . . . , x4) = Σm(6, 7, 8, 10, 12, 14, 15). Assume that the input variables are available in both uncomplemented and complemented forms.
Repeat Problem 8.29 for the function f (x1, . . . , x4) = Σm(2, 3, 4, 5, 9, 10, 11, 12, 13, 15).Data From Problem 8.29Find the minimum-cost circuit consisting only of two-input NOR gates for the function f (x1, . . . , x4) = Σm(6, 7, 8, 10, 12, 14, 15). Assume that the input variables are
Write Verilog code that represents an eight-bit Johnson counter. Synthesize the code with your CAD tools and give a timing simulation that shows the counting sequence.
Figure 5.4 shows a latch built with NOR gates. Draw a similar latch using NAND gates. Derive its characteristic table and show its timing diagram. R S R Qb S 0 1 0 Qa 0 0 Da Do (a) Circuit 11 12 Qa 13 14 15 SR 16 0 0 1 1 17 0 (c) Timing diagram 1 0 1 (b) Characteristic table QaQb 0/1 1/0 (no
The gated SR latch in Figure 5.5a has unpredictable behavior if the S and R inputs are both equal to 1 when the Clk changes to 0. One way to solve this problem is to create a set-dominant gated SR latch in which the condition S = R = 1 causes the latch to be set to 1. Design a set-dominant gated SR
Consider the circuit in Figure P5.2. Assume that the two NAND gates have much longer (about four times) propagation delay than the other gates in the circuit. How does this circuit compare with the circuits that we discussed in this chapter? A B D D D D E
Show a circuit that implements the gated SR latch using NAND gates only.
Given a 100-MHz clock signal, derive a circuit using D flip-flops to generate 50-MHz and 25-MHz clock signals. Draw a timing diagram for all three clock signals, assuming reasonable delays.
An SR flip-flop is a flip-flop that has set and reset inputs like a gated SR latch. Show how an SR flip-flop can be constructed using a D flip-flop and other logic gates.
Show how a JK flip-flop can be constructed using a T flip-flop and other logic gates.
Write Verilog code that represents a T flip-flop with an asynchronous clear input. Use behavioral code, rather than structural code.
Write Verilog code that represents a JK flip-flop. Use behavioral code, rather than structural code.
Synthesize a circuit for the code written for Problem 5.10 by using your CAD tools. Simulate the circuit and show a timing diagram that verifies the desired functionality. Clock D Qa Qb Qc D Clock D Q Cik Q D Q D (a) Circuit 10 Q (b) Timing diagram Qa Qc Qc
Design a four-bit synchronous counter with parallel load. Use T flip-flops, instead of the D flip-flops used in Section 5.9.3.Section 5.9.3Counters with Parallel Load Often it is necessary to start counting with the initial count being equal to 0. This state can be achieved by using the
A universal shift register can shift in both the left-to-right and right-to-left directions, and it has parallel-load capability. Draw a circuit for such a shift register.
Consider the circuit in Figure P5.4. How does this circuit compare with the circuit in Figure 5.16? Can the circuits be used for the same purposes? If not, what is the key difference between them? Clock D S Q CIK R Q S CIK Q 10 R Q ē
Write Verilog code for a universal shift register with n bits.
The circuit in Figure P5.3 looks like a counter. What is the counting sequence of this circuit? 1 Clock T Q Qo T Q Q₁ T Q Q₂
For the flip-flops in the counter in Figure 5.24, assume that tsu = 3 ns, th = 1 ns, and the propagation delay through a flip-flop is 1 ns. Assume that each AND gate, XOR gate, and 2-to-1 multiplexer has the propagation delay equal to 1 ns. What is the maximum clock frequency for which the circuit
Design a three-bit up/down counter using T flip-flops. It should include a control input called U̅p/Down. If U̅p/Down = 0, then the circuit should behave as an up-counter. If U̅p/Down = 1, then the circuit should behave as a down-counter.
Construct a NOR-gate circuit, similar to the one in Figure 5.11a, which implements a negative-edge-triggered D flip-flop. Clock D D 2 3 P3 P4 P1 P2 (a) Circuit 5 6 Q Q
Repeat Problem 5.15 using D flip-flops.Data From Problem 5.15Design a three-bit up/down counter using T flip-flops. It should include a control input called U̅p/Down. If U̅p/Down = 0, then the circuit should behave as an up-counter. If U̅p/Down = 1, then the circuit should behave as a
A ring oscillator is a circuit that has an odd number, n, of inverters connected in a ring like structure, as shown in Figure P5.5. The output of each inverter is a periodic signal with a certain period.(a) Assume that all the inverters are identical; hence they all have the same delay, called tp.
Write Verilog code in the style shown in Figure 5.51 that represents a ring counter. Your code should have a parameter n that sets the number of flip-flops in the counter. module shiftn (R, L, w, Clock, Q); parameter n = 16; input [n-1:0] R; input L, w, Clock; output reg [n-1:0] Q; integer
Write Verilog code that represents a modulo-12 up-counter with synchronous reset.
The following code checks for adjacent ones in an n-bit vector.With blocking assignments this code produces the desired logic function, which is f = a1a0 +· · ·+an−1an−2. What logic function is produced if we change the code to use non-blocking assignments? always @(A) begin f = A[1] &
A circuit for a gated D latch is shown in Figure P5.7. Assume that the propagation delay through either a NAND gate or an inverter is 1 ns. Complete the timing diagram given in the figure, which shows the signal values with 1 ns resolution. Clock 1 0 D A O 0 0 D Clock D Dx Q
A logic circuit has two inputs, Clock and Start, and two outputs, f and g. The behavior of the circuit is described by the timing diagram in Figure P5.8. When a pulse is received on the Start input, the circuit produces pulses on the f and g outputs as shown in the timing diagram. Design a suitable
The Verilog code in Figure P5.9 represents a 3-bit linear-feedback shift register (LFSR).This type of circuit generates a counting sequence of pseudo random numbers that repeats after 2n − 1 clock cycles, where n is the number of flip-flops in the LFSR. Synthesize a circuit to implement the LFSR
Repeat Problem 5.28 for the Verilog code in Figure P5.10.Data From Problem 28The Verilog code in Figure P5.9 represents a 3-bit linear-feedback shift register (LFSR).This type of circuit generates a counting sequence of pseudo random numbers that repeats after 2n − 1 clock cycles, where n is the
The Verilog code in Figure P5.12 is equivalent to the code in Figure P5.10, except that blocking assignments are used. Draw the circuit represented by this code. What is its counting sequence? module Ifsr (R, L, Clock, Q); input [0:2] R; input L, Clock; output reg [0:2] Q; always @(posedge
The circuit in Figure 5.59 gives a shift register in which the parallel load control input is independent of the enable input. Show a different shift register circuit in which the parallel-load operation can be performed only when the enable input is also asserted. W Clock E R₁-1
Derive a circuit that realizes the FSM defined by the state-assigned table in Figure P6.1 using JK flip-flops. Present state 92/1 00 01 10 11 Next state W = 0 Y2Y1 10 01 11 a 10 W = 1 Y2Y1 11 00 00 01 Output Z 0 0 0 1
An FSM is defined by the state-assigned table in Figure P6.1. Derive a circuit that realizes this FSM using D flip-flops. Present state 2.31 00 01 10 11 Next state W = 0 Y2Y1 10 01 11 10 W = 1 Y2Y1 11 00 00 01 Output Z 0 0 0 1
The Verilog code in Figure P5.11 is equivalent to the code in Figure P5.9, except that blocking assignments are used. Draw the circuit represented by this code. What is its counting sequence? module Ifsr (R, L, Clock, Q); input [0:2] R; input L, Clock; output reg [0:2] Q: always @(posedge Clock) if
Derive the state diagram for an FSM that has an input w and an output z. The machine has to generate z = 1 when the previous four values of w were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are allowed. An example of the desired behavior is w : 010111100110011111z :
Write Verilog code for the FSM described in Problem 6.3.Data From Problem 6.3.Derive the state diagram for an FSM that has an input w and an output z. The machine has to generate z = 1 when the previous four values of w were 1001 or 1111; otherwise, z = 0. Overlapping input patterns are allowed. An
Derive the circuits that implement the state tables in Figures 6.51 and 6.52. What is the effect of state minimization on the cost of implementation? Present state A B C D E F G Next state w = 0 w = 1 B D F B F E F CF с E G с D G Output Z 1 1 1 0 0
Derive a minimal state table for a single-input and single-output Moore-type FSM that produces an output of 1 if in the input sequence it detects either 110 or 101 patterns. Overlapping sequences should be detected.
Derive the circuits that implement the state tables in Figures 6.55 and 6.56. Compare the costs of these circuits. Present state S1 S2 S3 S4 S5 S6 S7 S8 S9 Next state DN = 00 01 10 S1 S3 S3 S2 S2 S5 S3 S7 S1 S3 S6 S8 S9 S1 S1 S3 S4 S4 S6 S6 - - - 11 Output Z 0 0 0 1 1 0 1 1 1
Repeat Problem 6.5 for a Mealy-type FSM.Data From Problem 6.5.Derive a minimal state table for a single-input and single-output Moore-type FSM that produces an output of 1 if in the input sequence it detects either 110 or 101 patterns. Overlapping sequences should be detected.
Write Verilog code for the FSM described in Problem 6.9.Data From Problem 6.9.A sequential circuit has two inputs, w1 and w2, and an output, z. Its function is to compare the input sequences on the two inputs. If w1 = w2 during any four consecutive clock cycles, the circuit produces z =
A given FSM has an input, w, and an output, z. During four consecutive clock pulses, a sequence of four values of the w signal is applied. Derive a state table for the FSM that produces z = 1 when it detects that either the sequence w : 0010 or w : 1110 has been applied; otherwise, z = 0. After the
Draw timing diagrams for the circuits in Figures 6.43 and 6.47, assuming the same changes in a and b signals for both circuits. Account for propagation delays. a b Full adder Y carry-out Clock Reset D Q 10 S
Derive a minimal state table for an FSM that acts as a three-bit parity generator. For every three bits that are observed on the input w during three consecutive clock cycles, the FSM generates the parity bit p = 1 if and only if the number of 1s in the three-bit sequence is odd.
Show a state table for the state-assigned table in Figure P6.1, using A, B, C,D for the four rows in the table. Give a new state-assigned table using a one-hot encoding. For A use the code y4y3y2y1 = 0001. For states B, C,D use the codes 0010, 0100, and 1000, respectively. Synthesize a circuit
Write Verilog code for the FSM described in Problem 6.12.Data From Problem 6.12.Derive a minimal state table for an FSM that acts as a three-bit parity generator. For every three bits that are observed on the input w during three consecutive clock cycles, the FSM generates the parity bit p = 1 if
Show how the circuit derived in Problem 6.15 can be modified such that the code y4y3y2y1 = 0000 is used for the reset state, A, and the other codes for stateB, C,Dare changed as needed.Data From Problem 6.15Show a state table for the state-assigned table in Figure P6.1, using A, B, C,D for the four
In Figure 6.59 assume that the unspecified outputs in states B andG are 0 and 1, respectively. Derive the minimized state table for this FSM. Present Next Output state state Z2Z1Z0 ABCDEFGE Ε H B C DEFGHA 000 100 010 110 001 101 011 111

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