Questions and Answers of Analysis and Design Integrated Circuits

Repeat Problem 7.3 for the MOS circuit in Problem 7.2.Data from Prob. 7.3:Calculate an expression for the output impedance of the circuit in Problem 7.1 as seen by RL and form an equivalent circuit.
Repeat Problem 7.3 for RS= 0 and RS= ˆž.Data from Prob. 7.3:Calculate an expression for the output impedance of the circuit in Problem 7.1 as seen by RL and form an equivalent circuit. Plot
Calculate an expression for the output impedance of the circuit in Problem 7.1 as seen by RL and form an equivalent circuit. Plot the magnitude of this impedance on log scales from f = 1 kHz to f =
Repeat Problem 7.1 for the MOS commonsource stage shown in Fig. 7.2b using RS= 10 kÎ©, RL= 5 kÎ©, ID= 0.5 mA, and the following NMOS transistor data: NMOS: W = 100 µm,
(a) Use the Miller approximation to calculate the ˆ’3-dB frequency of the small-signal voltage gain of a common-emitter transistor stage as shown in Fig. 7.2a using RS= 5 kÎ©,
In BiCMOS technology, MOS source followers can be used to drive a bipolar differential pair to reduce the average current flowing in the stage input leads. See Fig. 6.64. Calculate the input-referred
Find the minimum value of VCC for proper operation of the NE5234 op amp. For simplicity, assume VEE= 0, |VBE(on)| = 0.7 V, and |VCE(sat)| = 0.1 V. Also, ignore base currents. Assume the bias circuits
(a) Suppose that the npn and pnp transistors in the input stage of the NE5234 op amp are changed into n-channel and p-channel MOS transistors, respectively. If transistors conducting nonzero current
Repeat Problem 6.29 except replace each pnp transistor with a p-channel MOS transistor and replace each npn transistor with an n-channel MOS transistor. Assume Vt= 0.5 V and Vov= 0.1 V for all
Find the small-signal voltage gain of the NE5234 op amp under the same conditions given in this chapter except use βF(npn) =β0(npn) = 80 and βF(pnp) = β0(pnp) = 20. Ignore βF(npn) and βF(pnp)
Calculate the low-frequency PSRR from the Vdd andVss power supplies for the common-source amplifier shown in Fig. 6.57. Assume the transistor is biased in the active region.Figure 6.57 VDD + Vdd ER
For the circuit of Fig. 6.53, determine the output current as a function of the input voltage. Assume that the transistor operates in the active region.Figure 6.53 lout Ideal Vin
In Fig. 6.31b, resistive loads were used to extend the common-mode input range to include ˆ’VEE. Fig. 6.62 shows another circuit with this characteristic. Find the common-mode range of this
Determine the small-signal voltage gain of the NE5234 if all the values of all the resistors in the input stage are doubled. Assume the common-mode input voltage is low enough that Q1 and Q2 are off.
Fig. 6.61 shows an alternate scheme for biasing the NE5234 output stage.Ignoring all base currents, find |IC74| IC75. Use Fig. 6.42 for the relative emitter areas of all the transistors except assume
Assume that Q75 does not saturate and calculate the maximum value of IC75 in the NE5234 op amp. Assume VEB70(on) = 0.7 V, IS71 = 6 × 10−18 A and IS75 = 6×10−17 A.
(a)Figure 6.60a shows a folded version of the op amp in Fig. 6.15. A differential inter stage level-shifting network composed of voltage sources V has been inserted between the first and second
Suppose that the peak-peak output swing requirement in Problem 6.22 is reduced while the other conditions are held constant. This change allows the overdrive magnitude to be increased. Which
For the folded-active-cascode op amp in Fig. 6.30, choose the device sizes to give a peak-peak output swing of at least 2.5 V. Use the 0.4 Î¼m CMOS model parameters in Table 2.4 except
Draw the schematic of a folded-cascode op amp similar to the op amp in Fig. 6.28 except with two layers of both n- and p-type cascodes. Choose a current mirror that maximizes the output swing. Assume
Design a CMOS op amp based on the folded-cascode architecture of Fig. 6.28 using supply voltages of ± 1.5 V. Use the bias circuit of Fig. 4.42 (with M3and M4cascoded) to generate the
Find the low-frequency voltage gain from variation on each power supply to the op-amp out-put in Fig. 6.28. Assume that the bias voltages VBIAS1, VBIAS2, and VBIAS3are produced by the circuit shown
Calculate the common-mode input range of the folded-cascode op amp in Fig. 6.28. Assume that all the transistors are enhancement-mode devices with |Vt|=1 V, and ignore the body effect. Also assume
Draw a telescopic-cascode op amp similar to the first stage in Fig. 6.25 except use an n-channel input pair and a high-swing p-type cascode current-mirror load. Calculate the maximum output swing in
Calculate the common-mode input range of the op amp in Fig. 6.25. Assume that all the transistors are enhancement-mode devices with |Vt| = 1V,and ignore the body effect. Also assume that the biasing
Calculate bias currents and the low-frequency small-signal voltage gain for the CMOS op amp of Fig. 6.58. Use the parameters given in Table 2.4, and assume that Xd=0.1 Î¼m and
List and explain at least three reasons to select a two-stage op amp with an n-channel input pair instead of with a p-channel input pair for a given application.
(a) Calculate the random input offset voltage for the op amp in Fig. 6.16. Assume the matching is perfect except thatVt3ˆ’Vt4= 10mV. Also assume that all transistors have equal W/Land
(a) Equation 6.69 gives the random input off-set voltage of the op amp in Fig. 6.16. Explain the polarity of each term in (6.69) by assuming that the matching is perfect except for the term under
Draw a two-stage op amp similar to the op amp in Fig. 6.16 except reverse the polarity of every transistor. For example, the resulting op amp should have an n.-channel input pair. Calculate the
(a) Calculate and sketch the output voltage waveform of the switched-capacitor integrator of Fig. 6.10a from t =0 to t =20 Î¼s assuming a fixed Vs = 1 V and a clock rate of 1 MHz. Assume
In the switched-capacitor amplifier of Fig. 6.9a, assume that the source of M4is connected to VSinstead of to ground. Calculate the output volt-age that appears during Ï†2for a given VS.
Suppose an op amp with PSRR+= 10 is con-nected in the voltage-follower configuration shown in Fig. 6.3c. The input VSis set to zero, but a low- fre-quency ac signal with peak magnitude Vsup=20 mV is
Consider the differential amplifier shown in Fig. 6.4. Choose values of R1and R2for which the gain is equal toˆ’10 and the magnitude of the dc output voltage is less than or equal
Once the offset voltage of the differential amplifier in Problem 6.4 is adjusted to zero, the input-referred offset voltage must remain less than 1 mV in magnitude for common-mode input voltages
The differential instrumentation amplifier shown in Fig. 6.56 must have a voltage gain of 103 with an accuracy of 0.1 percent. What is the minimum required open-loop gain of the op amp? Assume
In the circuit of Fig. 6.55, determine the cor-rect value ofRxso that the output voltage is zero when the input voltage is zero. Assume a nonzero input bias current, but zero input offset current and
Determine the output voltage as a function of the input voltage for the circuit of Fig. 6.54. Assume the op amp is ideal.Figure 6.54 1 k2 1 ΚΩ Vout +0 Vin
Using the schematics from Fig. 5.35 and Problem 5.24, design the output stage shown in Fig. 5.32 to satisfy the following requirements.(a) VDD = VSS = 2.5 V.(b) The standby power dissipation should
Using a circuit that is the complement of the one in Fig. 5.35, draw the schematic for the bottom error amplifier and output transistor M2, which are shown in block diagram form in Fig. 5.32. In the
For the circuit in Fig. 5.34, assume that the input voltage Viis high enough that M1operates in the active region but M2is cut off. Using the same assumptions as in the derivation of (5.116), show
Design a CMOS output stage based on the circuit of Fig. 5.31 to deliver ±1 V before clipping at Vowith RL = 1 kÎ© and VDD= VSS= 2.5 V. Use 10 µA bias current in
Find the minimum output voltage for the circuit in Fig. 5.31.Figure: 5.31: VDp BIAS Mз M4 M4 RL M2 M5 M6 +o -Vss
A BiCMOS Class AB output stage is shown in Fig. 5.43. Device parameters are Î²F(npn) = 80, Î²F(pnp) = 20, VBE(on)= 0.8 V, Î¼pCox= 26 µA/V2, and Vt=
For the circuit of Fig. 5.25, assume that VCC= 15V, Î²F(pnp) = 30, Î²F(npn) = 150, IS(npn) = 10ˆ’14A, IS(pnp) = 10ˆ’15A, and for all devices VBE(on)= 0.7 V, VCE(sat)= 0.2 V. Assume that
An all-npn Darlington output stage is shown in Fig. 5.42. For all devices VBE(on)= 0.7 V, VCE(sat)= 0.2 V, Î²F= 100. The magnitude of the collector current in Q3is 2 mA.(a) If RL = 8
For the circuit of Problem 5.15, calculate bias currents in Q23,Q20, Q19, Q18, and Q14for Vo= ˆ’10 V with RL= 1 kÎ©. Use IS= 10ˆ’14A for all devices.Data from Prob.
(a) For the circuit of Problem 5.15, calculate the maximum possible average output power than can be delivered to a load RLif the instantaneous power dissipation per device must be less than 100 mW.
For the output stage of Fig. 5.20a, assume that VCC= 15 V, Î²F(pnp) = 50, Î²F(npn) = 200, and for all devices VBE(on)= 0.7 V, VCE(sat)= 0.2 V, IS= 10ˆ’14A. Assume that
For the output stage of Fig. 5.18, assume that VCC= 15 V and for all devices VCE(sat)= 0.2 V, VBE(on)= 0.7 V, and Î²F= 50.Fig. 5.18:(a) Calculate the maximum positive and negative limits
In the circuit of Fig. 5.13, VCC= 12 V, IQ= 0.1 mA, RL= 1 kÎ©, and for all devices IS= 10ˆ’15A, Î²F= 150. Calculate the value of Viand the current in each device for
For the circuit of Problem 5.10, calculate and sketch the waveforms of Ic1, Vce1, and Pc1for device Q1over one cycle. Do this for output voltage amplitudes (zero to peak) of 11.5 V, 6 V, and 3 V.
For the circuit of Fig. 5.10, assume that VCC= 12 V, RL= 1 kÎ©, and VCE(sat)= 0.2 V. Assume that there is sufficient sinusoidal input voltage available at Vito drive Voto its limits of
The circuit of Fig. 5.10 has VCC= 15 V, RL= 2 kÎ©, VBE(on)= 0.6 V, and VCE(sat)= 0.2 V.(a) Sketch the transfer characteristic from Vi to Vo assuming that the transistors turn on abruptly
Calculate second-harmonic distortion in the common-source amplifier with a depletion load shown in Fig. 4.20a for a peak sinusoidal input voltage vÌ‚i= 0.01 V and VDD= 3 V. Assume that the dc
When the distortion is small, the second and third harmonic-distortion terms of an amplifier can be calculated from the small-signal gains at the quiescent and extreme operating points. Starting with
Calculate the incremental slope of the transfer characteristic of the circuit of Fig. 5.8 at the quiescent point and at the extremes of the signal swing with vi= vÌ‚isin Ï‰t and
(a) For the circuit of Problem 5.1, draw load lines in the Ic - Vce plane for RL = 0 and RL→ ∞. Use an Ic scale from 0 to 30 mA. Also draw constant power hyperbolas for Pc = 0.1 W, 0.2
Calculate the incremental slope of the transfer characteristic of the circuit of Problem 5.1 at the quiescent point and at the extremes of the signal swing with a peak sinusoidal output of 1 V and
If Î²F= 100 for Q1in Problem 5.1, calculate the average signal power delivered to Q1by its driver stage if Vois sinusoidal with an amplitude equal to the maximum possible before clipping
(a) Prove that any load line tangent to a power hyperbola makes contact with the hyperbola at the midpoint of the load line.(b) Calculate the maximum possible instantaneous power dissipation in Q1
(a) For the circuit of Problem 5.1, sketch load lines in the Ic- Vceplane for RL= 2 k„¦ and RL= 10 k„¦.(b) Calculate the maximum average sinusoidal output power that can be
A circuit as shown in Fig. 5.1 has VCC= 15V, R1= R2= 0, R3= 5k„¦, RL= 2k„¦, VCE(sat)= 0.2 V, and VBE(on)= 0.7 V. All device areas are equal.(a). Sketch the transfer
Repeat Problem 4.38 but replace the bipolar transistors with MOS transistors as in Problem 4.14. Assume the worst-case W/L mismatches in the transistors are ± 5 percent and the worst-case
Repeat Problem 4.38, but assume that 2-kÎ© resistors are placed in series with the emitters of Q3and Q4. Assume the worst-case resistor mismatch is ± 0.5 percent and the worst-case
Determine the worst-case input offset voltage for the circuit of Fig. 4.58. Assume the worst-case ISmismatches in the transistors are ± 5 percent and Î²F= 15 for the pnp
A pair of bipolar current sources is to be designed to produce output currents that match with ± 1 percent. If resistors display a worst-case mismatch of ± 0.5 percent, and transistors a worst-case
For the bias circuit shown in Fig. 4.66, determine the bias current. Assume that Xd= Ld= 0. Neglect base currents and the body effect. Comment on the temperature dependence of the bias current.
The circuit of Fig. 4.65 produces a supplyinsensitive current. Calculate the ratio of small-signal variations in IBIASto small-signal variations in VDDat low frequencies. Ignore the body effect but
Calculate the bias current of the circuit shown in Fig. 4.65 as a function of R, Î¼nCox, (W/L)1, and (W/L)2. Comment on the temperature behavior of the bias current. For simplicity,
For the circuit of Fig. 4.64, find the value of W/L for which dVGS/dT = 0 at 25 °C. Assume that the threshold voltage falls 2 mV for each 1°C increase in temperature. Also, assume that the
Aband-gap reference circuit is shown in Fig. 4.63. Assume that Î²F†’ ˆž, VA†’ˆž, IS1= 1 Ã— 10ˆ’15A, and IS2= 8 Ã—
Repeat Problem 4.29 assuming that the values of IS, R2, and R1are nominal but that R3is 1 percent low. Assume VBE(on)= 0.6 V.Data from Prob. 4.29:A band-gap reference like that of Fig. 4.47 is
Simulate the band-gap reference from Problem 4.29 on SPICE. Assume that the amplifier is just a voltage-controlled voltage source with an openloop gain of 10,000 and that the resistor values are
A band-gap reference like that of Fig. 4.47 is designed to have nominally zero TCFat 25°C. Due to process variations, the saturation current ISof the transistors is actually twice the nominal
The circuit of Fig. 4.46c is to be used as a band-gap reference. If the op amp is ideal, its differential input voltage and current are both zero andVOUT = (VBE1 + I1R1) = (VBE1 + I2R2)VOUT =
In the analysis of the hypothetical reference of Fig. 4.44, the current I1was assumed proportional to temperature. Assume instead that this current is derived from a diffused resistor, and thus has a
Determine the value of sensitivity S of output current to supply voltage for the circuit of Fig. 4.62, where S = (VCC/IOUT)(ˆ‚IOUT/ˆ‚VCC).Fig. 4.62: Vcc= 15 V |IOUT 10 k2 R1 Q2 1
Determine the output current and output resistance of the circuit shown in Fig. 4.61.Fig. 4.61: + 15 V 13.7 k2 |'OUT Q2 700 2
Design the MOS peaking current source in Fig. 4.34 so that IOUT= 0.1 µA.(a) First, let IIN = 1 µA and find the required value of R.(b) Second, let R = 10 kÎ© and find the
Design a MOS Widlar current source using the circuit shown in Fig. 4.31b to meet the following constraints with VDD= 3 V:(a) The input current should be 100 µA, and the output current should be
Determine the output current in the circuit of Fig. 4.60.Fig. 4.60: Vcc= 15 V 20 kΩ 1ουτ Q1 Q2 10 kΩ
In the design of a Widlar current source of Fig. 4.31 a to produce a specified output current, two resistors must be selected. Resistor R1sets IIN, and the emitter resistor R2sets IOUT. Assuming a
Design a Widlar current source using npn transistors that produces a 5 µA output current. UseFig. 4.31a with identical transistors, VCC = 30 V, and R1 = 30 kÎ©. Find the output
Although Gm [cm] of a differential pair with a current-mirror load can be calculated exactly from a small-signal diagram where mismatch is allowed, the calculation is complicated because the
Find Gm[dm] of a source-coupled pair with a current-mirror load with nonzero mismatch (Fig. 4.29b) and show that it is approximately given by (4.184). Calculate the value of Gm[dm] using the
Repeat Problem 4.16 except replace the npn and pnp transistors with n-channel and p-channel MOS transistors, respectively. Assume Wn= 50[1]µm and Wp= 100[1]µm. For all transistors, assume
Determine the unloaded voltage gain Î½o/Î½iand output resistance for the circuit of Fig. 4.59. Neglect rÎ¼. Verify with SPICE and also use SPICE to plot the
Repeat Problem 4.14, but now assuming that 2 k„¦ resistors are inserted in series with the sources of M3and M4. Ignore the body effect?Repeat Problem 4.14:Determine the unloaded voltage
Repeat Problem 4.12 except replace Q1and Q2with n-channel MOS transistors M1and M2. Also, replace Q3and Q4with p-channel MOS transistors M3and M4. Assume Wn= 50[1]m and Wp= 100 µm.Repeat
Repeat Problem 4.12, but now assuming that 2-k„¦ resistors are inserted in series with the emitters of Q3and Q4.Repeat Problem 4.12:Determine the unloaded voltage gain
Determine the unloaded voltage gain Î½o/Î½iand output resistance for the circuit of Fig. 4.58. Check with SPICE and also use SPICE to plot out the large-signal VO-VItransfer
Calculate the small-signal voltage gain of a common-source amplifier with depletion load in Fig. 4.20, including both the body effect and channel-length modulation. Assume that VDD= 3 V and that the
Calculate the small-signal voltage gain of the common-source amplifier with active load in Fig. 4.16b.Assume that VDD= 3 V and that all the transistors operate in the active region. Do the
Calculate the output resistance of the Wilson current mirror shown in Fig. 4.57. What is the percentage change in IOUTfor a 5-V change in VOUT? Compare your answer with a SPICE simulation using a
For the circuit of Fig. 4.56, assume that (W/L)8= (W/L). Ignoring the body effect, find (W/L)6and (W/L)7so that VDS6 = VDS7= Vov8. Draw the schematic of a double-cascode current mirror that uses
Design the circuit of Fig. 4.11b to satisfy the constraints in Problem 4.3 except the output resistance objective is that the output current change less than 0.02 percent for a 1 V change in the
Using the data given in the example of Section 1.9, include the effects of substrate leakage in the calculation of the output resistance for the circuit of Problem 4.5. Let VOUT= 2Vand 3V?Data from
Calculate the output resistance of the circuit of Fig. 4.9, assuming that IIN=100 ÂµA and the devices have drawn dimensions of 100 Âµm/1 Âµm. Use the process parameters given in Table 2.4, and
Calculate an analytical expression for the small-signal output resistance Roof the bipolar cascode current mirror of Fig. 4.8. Assume that the input current source is not ideal and that the

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