Questions and Answers of Analysis and Design Integrated Circuits

For the op amp in Fig. 12.2, use the device data and operating point from the first example in Section 12.4.1. Assume all transistors operate in the active region. (a) Find the element values in
For the op amp in Fig. 12.2, use the data from Problem 12.4 except use ID5= 100 µA and |Vov| = 0.1 V for all transistors. Assume all transistors operate in the active region with Cgs= 180 fF
(a) For the op amp in Problem 12.5, calculate a€™cm. Assume that the CMFB scheme in Fig. 12.17 is used and that acms= 1. Recall that a€™cm= voc/vicwhen the CMFB loop is active.(b)
The op amp in Problem 12.5 is connected in feedback as shown in Fig. 12.32 a. The CMFB is as described in Problem 12.6. Compute the low-frequency closed-loop gains Adm= vod/vsdand Acm =
Calculate the DM output slew rate dVod/dt for the op amp in Fig. 12.2. Assume ID5= 200 µA and a 5 - pF capacitor is connected from each op-amp output to ground.Fig. 12.2: Vpp VBIAS M4 Мз Vo2
Calculate the CM output slew rate dVoc / dt for the op amp in Fig. 12.2. Assume ID5= 200 µA and a 5€“pF capacitor is connected from each op-amp output to ground.Figure 12.2: Vpp
Compute the output slew rate dVod / dt for the op amp in the example in Section 12.6.1. Use the bias currents from the example and C = 1.39 pF.
For this problem, use the op amp in Fig. 12.23 and the CMFB scheme in Fig. 12.17. Use the complement of the amplifier in Fig. 12.16b as the CM-sense amplifier, modified to give a negative dc gain.
Compute the op-amp CM and DM load capacitances for the output loading in Fig. 12.53 a and 12.53 b. Assume the inverting voltage buffers in Fig. 12.53 b are ideal.Figure 12.53 (a):Figure 1253 (b): Vo1
(a) For the amplifier in Fig. 12.16 b, estimate the pole associated with the RC time constant at the Vcmsoutput node. Assume |ID25| = 0.4 mA, Vov23= 0.2 V, and VOC= VCM. Ignore all capacitances
A differential amplifier with local CMFB is shown in Fig. 12.54. Use |Vov| = 0.2 V for all transistors, Vtn= ˆ’Vtp= 0.6 V, ID5= 200 µA, VAn= 10 V, |VAp| = 20 V, and Î³ = 0.
A differential amplifier that does not use a tail current source is shown in Fig. 12.55.(a) Compute the low-frequency gains adm and acm. For all transistors, drain currents are 100 µA and |Vov|
(a) For the op amp in Fig. 12.2, assume the CM and DM load capacitances are CLc= CLd= 2 pF. Calculate the frequencies at which |adm(jÏ‰) | = 1 and |acmc(jÏ‰) | = 1, ignoring other
For the CM-detector in Fig. 12.56, find acms(s) = vcms(s) / voc(s), assuming the CM-sense amplifier is ideal with unity gain. Then find acms(s) when a capacitor Ccsis connected in parallel with each
A NMOS transistor is operating in the triode region. Find a formula for its transconductance gm = ∂Id / ∂Vgs. Compare it with gm in the active region at the same dc drain current. Which
For the fully differential circuit in Fig. 12.32 a, assume the op amp is ideal with Ri= ˆž, Ro= 0, adm= ˆ’ ˆž, and acm= 0. Find the closed-loop gains Adm= vod/vsd, Acm=
For the circuit in Problem 12.20 a, the applied source voltage is a single-ended signal with Vs1 = 0.2 V sin (100t) and Vs2 = 0. Assume a CMFB loop forces VOC = 0. What are Vo1 (t), Vo2 (t),
The op amp in Problem 12.4 is used with the CMFB scheme shown in Fig. 12.17. The circuit is perfectly balanced except that the CM-sense resistors are mismatched with the upper resistor Rcs1= 10.1
A fully differential op amp with CMFB is shown in Fig. 12.57. For M1, M1C, M2, and M2C, use W/L = (64 µm) / (0.8 µm). For M3 €“ M4, M26 €“ M27and M11, W / L
The feedback circuit in Fig. 12.58 is a switched-capacitor circuit during one clock phase. Assume the op amp is the folded-cascode op amp in Fig. 12.31.(a) Calculate the DM and CM output load
In the switched-capacitor CMFB scheme in Fig. 12.21, C1= 0.1 pF and C2= 0.5 pF.(a) With VCSBIAS = ˆ’1 V, VOC = VCM = 0.5 V. If VCSBIAS changes to ˆ’1.1 V, what is the new value of
A current-mirror op amp is shown in Fig. 12.59. Assume all NMOS transistors are matched and all PMOS transistors are matched. Use |Vov| = 0.2 V for all transistors, Vtn= ˆ’Vtp= 0.6 V, ID5=
Find the low-frequency value of a’cm for the two-stage op amp in the example in Section 12.6.1. Use the data in that example. Recall that a’cm = voc/vic when the CMFB loop is active.
Assume that the CMFB circuit in the example in Section 12.6.1 is changed so that the CM-sense amplifier has a low-frequency gain |acms0| = 2.5. Determine the compensation capacitor C needed in the op
Neutralization capacitors Cn are to be added to cancel the Miller effect on Cgd1 and Cgd2 in the two-stage op amp in the example in Section 12.6.1.(a) Show how the Cn capacitors should be
Modify the CMFB schematic in Fig. 12.26 to inject currents at the drains of M1and M2, in a manner similar to that shown in Fig. 12.18. Give a set of bias current values on the schematic. Assume
A fully differential op amp with mismatch is connected in the feedback circuit in Fig. 12.32a With R1= R2=10 kÎ© and R3= R4= 40 kÎ©. The op amp model is shown in Fig. 12.37
For the op amp in Fig. 12.40, what is the common-mode input range (CMIR) if only M1and M2are changed to low-threshold devices with threshold voltages Vt1= Vt2= 0.3V?Fig. 12.40: VDD M12 M11 BiasB
For the op amp in Fig. 12.40, what are the output voltage swing limits of Vo1 and Vo2if the thresh-old voltages of only M1A, M2A, M3A, and M4Aare changed toVt1A= Vt2A= ˆ’0.3 V and
For the feedback circuit in Fig. 12.46, the capacitor values are C1 = C2 = 4 pF and CL = 6 pF. The op amp is the folded-cascode amplifier in Fig. 12.40 with low-frequency gainadm0=
For the feedback circuit in Fig. 12.46 using the op amp in Fig. 12.40, the capacitor values are C1= C2= 4 pF and CL = 6 pF. What is the differential-mode output slew rate?Fig. 12.46:Fig. 12.40:
For the feedback circuit in Fig. 12.46, C1= C2= 4 pF. The op amp is the folded-cascode amplifier in Fig. 12.40 with low-frequency gain adm0 = 1280 and gm1= 30 mA/V. What value of CLwill give
If W/Lis doubled for M1= M2(i.e., m1= m2= 20), what is the new low-frequency DM op-amp gain adm0for the op amp in Fig. 12.40? Assume the bias conditions and operating regions do not change.Fig.
Calculate the spectrum of the input-referred 1/f voltage noise for the op amp in Fig. 12.40.Use (11.69) with Kf = 4.8 Ã— 10ˆ’25 V2 €“F for NMOS devices and Kf = 8.3
Calculate the spectrum of the input-referred thermal noise voltage for the op amp in Fig. 12.40 if W/L is doubled for M1= M2(i.e., m1= m2= 20). Assume the bias conditions and operating regions are
A BiCMOS Darlington is shown in Fig. 11.51. Neglecting frequency effects, calculate the equivalent input noise voltage and current generators for this circuit, assuming that the dc value of Viis
Repeat Problem 9.9 if the circuit is compensated by using shunt capacitance to ground at the input of the second stage. Assume that this affects only the most dominant pole.Data from Prob. 9.9:An op
An op amp with low-frequency gain of 108 dB has three negative real poles with magnitudes 30 kHz, 500 kHz, and 10 MHz before compensation. The circuit is compensated by placing a capacitance across
An op amp has a low-frequency open-loop voltage gain of 100,000 and a frequency response with a single negative-real pole with magnitude 5 Hz. This amplifier is to be connected in a series-shunt
The amplifier of Problem 9.5 is to be compensated by reducing the magnitude of the most dominant pole.(a) Calculate the dominant-pole magnitude required for unity-gain compensation with 45° phase
An amplifier has a low-frequency forward gain of 5000 and its transfer function has three negative real poles with magnitudes 300 kHz, 2 MHz, and 25 MHz.(a) Calculate the dominant-pole magnitude
An amplifier has a low-frequency forward gain of 40,000 and its transfer function has three negative real poles with magnitudes 2 kHz, 200 kHz, and 4 MHz.(a) If this amplifier is connected in a
If an amplifier has a phase margin of 20°, how much does the closed-loop gain peak (above the low frequency value) at the frequency where the loop-gain magnitude is unity?
For the amplifier in Problem 9.1, calculate and sketch plots of gain (in decibels) and phase versus frequency (log scale) with no feedback applied. Determine the value of f that just causes
An amplifier has a low-frequency forward gain of 200 and its transfer function has three negative real poles with magnitudes 1 MHz, 2 MHz, and 4 MHz. Calculate and sketch the Nyquist diagram for this
Replace npn transistors Q1€“Q2in Fig. 8.49 with NMOS transistorsM1€“M2, and replace the pnp transistor Q3with PMOS transistor M3. Also, replace the 1.25 k resistor in the drain of
A feedback amplifier is shown in Fig. 8.49. Device data are as follows: Î²npn= 200, Î²pnp= 100, |VBE(on)| = 0.7V, rb= 0, and |VA| = ˆž. If the dc input voltage is
Repeat Problem 8.11 if the output signal is taken as the voltage at the emitter of Q3.Repeat Problem 8.11The half-circuit of a balanced monolithic series-series triple is shown in Fig. 8.18a.
The half-circuit of a balanced monolithic series-series triple is shown in Fig. 8.18a. Calculate the input impedance, output impedance, loop gain, and overall gain of the half-circuit at low
Repeat Problem 8.8 using the formulas from return-ratio analysis.Repeat Problem 8.8(a) Repeat Problem 8.7(a) with all NMOS transistors in Fig. 8.48 replaced by bipolar npn transistors. All collector
Repeat Problem 8.7 using the formulas from return-ratio analysis.Repeat Problem 8.7The ac schematic of a shunt-shunt feed-back amplifier is shown in Fig. 8.48. All transistors have ID = 1 mA,
(a) Repeat Problem 8.7(a) with all NMOS transistors in Fig. 8.48 replaced by bipolar npn transistors. All collector currents are 1 mA and Î² = 200,VA = 50 V, and rb=0.(b) If the circuit is
The ac schematic of a shunt-shunt feed-back amplifier is shown in Fig. 8.48. All transistors have ID= 1 mA, W/L = 100, k' = 60 Î¼A/V2, and Î» = 1/(50 V).(a) Calculate the
For the shunt-shunt feedback amplifier of Fig. 8.15a, take RF =100 kΩ and RL = 15 kΩ. For the op amp, assume that Ri =500 kΩ, Ro = 200, and av = 75,000. Calculate input resistance, output
Verify (8.43), (8.44), and (8.45) for a series-series feedback amplifier.(8.43)io/vi = a/1+af(8.44)Zi = zi(1 + T)(8.45)Zo = zo (1 + T)
Verify (8.40), (8.41), and (8.42) for a shunt-series feedback amplifier.(8.40)I0 /ii = a/ 1 + af(8.41)Zi = zi/1 + T(8.42)Z0 = z0 (1 + T)
(a) For the conditions in Problem 8.2(b), sketch the output voltage waveform So and the error volt-age waveform Sε if a sinusoidal input voltage Si with amplitude 1.5 V is applied.(b) Repeat (a)
For the characteristic of Fig. 8.2 the following data apply:So2 = 15 V So1 = 7V a1 = 50,000 a2 = 20,000(a) Calculate and sketch the overall transfer characteristic of Fig 8.3 for the above
(a) In a feedback amplifier, forward gain α = 100,000 and feedback factor f = 10−3. Calculate overall gain A and the percentage change in A if a changes by 10 percent.(b) Repeat (a) if f = 0.1.
Calculate the pole and zero associated with the current-mirror load in Fig. 7.33 if ID3= ˆ’100 µA, |Vov3| = 0.2 V, and Cx= 0.1 pF.Fig. 7.33: VDD Мз M4 V. х in- M2, in+ M1 ITAIL
Find an expression for Gm(s) = io(s)/Ï…id(s) for the circuit in Fig. 7.33 and verify the equations for the pole and zero given in Section 7.3.5.Fig. 7.33: VDD Мз M4 V. х in- M2, in+ M1
Add a 0.5 pF load capacitor from the output to ground to the integrator in Fig. 7.50. When this capacitor is added, the circuit has a loop of three capacitors. Direct application of the short-circuit
To calculate the dominant pole, calculate the open circuit time constants CinR = 0·2 Ã— 10€“12Ã— 20 Ã— 103= 4 Ã— 10€“9S(a)
(a) Use zero-value time constants to estimate the dominant pole and short-circuit time constants to estimate the nondominant pole for the common-source amplifier in Problem 7.2.(b) Compare your
(a) For the common-emitter amplifier in Problem 7.1, use zero-value time constants to estimate the dominant pole and short-circuit time constants to estimate the nondominant pole.(b) Compare your
AMOS cascode stage is shown in Fig. 7.43b. Replace the load resistor with a load capacitor CL= 2 pF. Assume the total capacitance that connects to the drain of M1 can be modeled by a capacitor Cp=
Use the short-circuit time-constant method to estimate the nondominant pole that originates at the drain nodes of M1and M2in the CMOS folded cascade of Fig. 6.28. Assume the gates of M1A, M2A, M5,
Repeat Problem 7.40 including short-channel effects with Îµc= 1.5 Ã— 106V/m.Data from Prob. 7.40:Use the zero-value time-constant method to estimate the small-signal dominant
Use the zero-value time-constant method to estimate the small-signal dominant pole for the current gain of the MOS cascode current mirror of Fig. 4.9. Assume an input ac current source in parallel
For the BiCMOS circuit of Fig. 3.78, use the zero-value time-constant method to estimate the first and second most dominant poles of the circuit. Assume an input voltage drive. Use bipolar transistor
A CMOS amplifier stage is shown in Fig. 7.49. Select W/L for M1and M5to give Vi= VO= 2.5V dc and |ID| = 100 µA bias in all devices. The minimum value of L and W is 2 µm. Calculate the
(a) A wideband MOS amplifier stage is shown in Fig. 7.48. Calculate the small-signal, low-frequency gain and use the zero-value timeconstant method to estimate the ˆ’3-dB bandwidth. Use
A two-stage bipolar amplifier is shown in Fig. 7.47. Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…iand use the zero-value time constant method to estimate
A two-stage amplifier is shown in Fig. 7.46. Calculate the low-frequency, small-signal gain and use the zero-value time-constant method to estimate the ˆ’3-dB frequency. Calculate the 10 to
Replace the MOS transistors in the amplifier in Fig. 7.45 with bipolar npn transistors. The emitter area of Q2is four times that of Q1and corresponding bias currents are IC1= 1 mA and IC2= 4 mA.
The ac schematic of a wideband MOS current amplifier is shown in Fig. 7.45. The W/L of M2is four times that of M1and corresponding bias currents are ID1= 1 mA and ID2= 4 mA. Calculate the
Repeat Problem 7.31 with n-channel MOS transistors replacing all bipolar transistors. Assume W = 100 µm, Ldrwn= 2 µm, Ld= 0.2 µm, Xd= 0, Î» = 0, k€™n= 60
An amplifier stage is shown in Fig. 7.44.(a) Calculate the low-frequency, small-signal voltage gain Ï…o/Ï…i.(b) Apply the zero-value time-constant method to the DM half-circuit to
Replace the NMOS transistors in Fig. 7.43 with npn transistors. The resulting ac schematics are of a common-emitter stage and a common-emitter€“common-base (cascode) stage. Repeat the
Repeat Problem 7.27, replacing the bipolar transistors with MOS transistors. Assume that the values of RB1 and RB2 set ID5 = 1 mA. Use W1 = W2 = W5 = W6 = 100 µm, W3 = W4 = 50 µm, and Ldrwn = 2
A differential circuit employing active loads is shown in Fig. 7.42. Bias voltage VBis adjusted so that the collectors of Q1and Q2are at +5 V dc. Biasing resistors are RB1= 10 kÎ© and RB2=
Repeat Problem 7.25 with the following changes:1. Replace Q1 with a p-channel MOS transistor, M1. Replace Q2 and Q3 with n-channel MOS transistors, M2 and M3.2. Add a resistor of value 1/gm1 from the
An amplifier stage is shown in Fig. 7.41 where bias current IBis adjusted so that VO= 0 V dc. Take VSUPPLY= 10 V.(a) Calculate the low-frequency, small-signal trans-resistance Ï…o/ii and
Repeat Problem 7.21 if a bleed resistor of 15 kÎ© is added from the emitter of Q1to ground, which increases the collector bias current in Q1to 50 µA.A Darlington stage and a
Replace the bipolar transistors in Fig. 7.40 with NMOS transistors. Repeat the calculations inProblem 7.21, using RS = 100 kÎ©, RL = 3 kÎ©, and the NMOS transistor model data in
Repeat Problem 7.21 if the input signal is a current source of value iiapplied at the base of Q1. (That is, iireplaces the voltage source Ï…iand resistance RS.) The transfer function is
A Darlington stage and a common-collector€“common-emitter cascade are shown schematically in Fig. 7.40, where RS= 100 kÎ© and RL= 3 kÎ©.(a) Calculate the low-frequency
Repeat Problem 7.18 if a resistor of value 50 kÎ© is connected between drain and gate of the transistor.Data from Prob. 7.18:Repeat Problem 7.14 using a NMOS transistor in place of the
Repeat Problem 7.18 if a 900 source-degeneration resistor is included in the circuit.Data from Prob. 7.18:Repeat Problem 7.14 using a NMOS transistor in place of the bipolar transistor. Use ID =
Repeat Problem 7.14 using a NMOS transistor in place of the bipolar transistor. Use ID= 0.5mA and the transistor data in Problem 7.2.Data from Prob. 7.14:The ac schematic of a common-emitter stage is
Repeat the calculations in Problem 7.14 for the common-source stage in Fig. 7.2b. Take VDB= 7.5 V and ID= 0.5 mA. Use the same transistor data and resistor values as in Problem 7.2 with the following
Repeat Problem 7.14 if an emitter degeneration resistor of value 300 is included in the circuit.Data from Prob. 7.14:The ac schematic of a common-emitter stage is shown in Fig. 7.2a. Calculate the
Repeat Problem 7.12 for a NMOS commongate stage using RL = 0 and RS = ∞. Use ID = 0.5 mA and the MOS transistor data in Problem 7.2. Plot the impedance magnitudes from f = 100 kHz to f = 100
A common-base stage has the following parameters: IC = 0.5 mA, Cπ = 10 pF, Cμ = 0.3 pF, rb = 200 Ω, β = 100, ro = ∞, RL = 0, and RS = ∞.(a) Calculate an expression for the small-signal
(a) Find expressions for R1, R2, and L in the output impedance model for a MOS source follower assuming RS ≫ 1/gm, γ ≠ 0, and υsb = υo.(b) Plot the magnitude of the output
For the source follower in Fig. 7.13b, find the low-frequency gain and plot the magnitude and phase of its voltage gain versus frequency from f = 10 kHz to f = 20 GHz, using log scales. Compare your
Calculate the values of the elements in the small-signal equivalent circuits for the input and output impedances of the emitter follower of Problem 7.8. Sketch the magnitudes of these impedances as a
A lateral pnp emitter follower has RS = 250 Ω, b = 200 Ω, β = 50, IC = −300 µA, fT = 4 MHz, RE = 4 kΩ, Cμ = 0, and ro = ∞. Calculate the small-signal voltage gain as a function of
A MOS differential amplifier is shown in Fig. 7.9. For this circuit, carry out the calculations in Problem 7.6. Use ISS= 1 mA, the values of RT= 300 kÎ© and CT= 2 pF as defined in Fig.
A bipolar differential amplifier as shown in Fig. 7.5 has IEE= 1 mA. The resistor values and transistor data are as given in Problem 7.1. If the tail current source has an associated resistanceRT=

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