Questions and Answers of Digital Systems Design

For the following SM chart,(a) Draw a timing chart that shows the clock, the state (S0, S1, or S2), the inputs (X1, X2, and X3), and the outputs. The input sequence is X1 X2 X3 = 011,
For the given SM chart,(a) Complete the following timing diagram (assume that X1 = 1, X2 = 0, X3 = 0, X5 = 1, and X4 is as shown). Flip-flops change state on falling edge of clock.(b) Using the
(a) Draw an SM chart that is equivalent to the state graph of Figure 4-46.(b) If the SM chart is implemented using a PLA and three flip-flops (A, B, C), give the PLA-table (state transition table).
(a) Write Verilog code that describes the following SM chart. Assume that state changes occur on the falling edge of the clock. Use two processes(b) The SM chart is to be implemented using a PLA and
Realize the following SM chart using a ROM with a minimum number of inputs, a multiplexer, and a loadable counter (like the 74163). The ROM should generate NST. The multiplexer inputs are selected as
Realize the SM chart of Problem 5.16 using the two-address microprogramming structure shown in Figure 5-29.(a) Convert the SM chart to the proper form by adding a minimum number of states to the
The following SM chart is to be realized using the two-address microprogramming structure shown in Figure 5-29.(a) Convert the SM chart to the proper form by adding a minimum number of states to the
(a) What are the conditions an SM chart must satisfy in order to realize it using single-address microprogramming with a counter, a ROM, and a multiplexer as in Fig 5-33?Figure 5-33: Microprogrammed
Realize the SM chart given here using a ROM, a counter, and a 4-to-1 multiplexer. (a) Draw a block diagram. Show the MUX inputs.(b) Change the SM chart to the proper form. Mark required changes
Realize the SM chart of Problem 5.20 using the two-address microprogramming hardware structure shown in Figure 5-29.(a) Convert the SM chart to the proper form by adding a minimum number of states to
The following SM chart is to be realized using single-address microprogramming.(a) Show the new SM chart and show the state assignments. The MUX inputs are 1, X1, X2, and X3. Do not invert inputs.
Given the following ASM chart,(a) Derive the next state and output equations, assuming the following state assignment:S0 = 00, S1 = 01, S2 = 10.(b) Convert the ASM chart to a form where it can be
The SM charts for three linked machines are given here. All state changes occur during the falling edge of a common clock. Complete a timing chart including ST, Wa, A, B, C, and D. All state machines
SM charts for two linked state machines are shown here. Machine T starts in state T0, and machine S starts in state S0. Draw a timing chart that shows CLK, the states of T and S, and signals P, R,
The SM charts for two linked state machines are given in the following diagram.(a) Complete the timing diagram shown here.(b) For the SM chart on the left, make a one-hot state assignment and derive
The SM chart for a simplified vending machine is shown here. The vending machine accepts only dimes and nickels. One soda costs 15 cents at this vending machine.D:Dime N:Nickel Z0:0cent
An 8-bit right-shift register with parallel load is to be implemented using an FPGA with logic blocks as shown in Figure 6-1(a). The flip-flops are labeled X7X6X5X4X3X2X1X0. The control signals N and
Implement a 2-bit binary counter using one logic block as shown in Figure 6-1(a). A0is the least significant bit, and A1is the most significant bit of the counter. The counter has a synchronous load
Design a 4-bit right-shift register using an FPGA with logic blocks as shown in Figure 6-1(a). When the register is clocked, the register loads if Ld = 1 and En = 1; it shifts right when Ld = 0 and
The next-state equations for a sequential circuit with two flip-flops (Q1and Q2), input signals R, S, T, and an output P areD1 = Q1+ = Q2R1 Q1S D2 = Q2+ = Q1+ Q2'TThe output equation is P = Q2RT
(a) Implement an 8-to-1 multiplexer using a minimum number of logic blocks of the type shown in Figure 6-1(a). Give the X and Y functions for each block and show the connections between blocks.(b)
(a) Write Verilog code that describes the logic block shown in Figure 6-1(a). Use the following module:module Figure6_1a(X_in,Y_in,clk,CE,Qx,Qy,X,Y,XLUT,YLUT);input[1:4]X_in,Y_in;input
(a) Write Verilog code that describes the logic block shown in Figure 6-3. Use a module similar to that used in Problem 6.6(a), except add ZLUT and SA, SB, SC, and SD. SA, SB, SC, and SD represent
(a) How many logic blocks as shown in Figure 6-1(a) are required to create a 4-to-16 decoder?(b) Give the contents of the LUTs in the first logic block.Figure 6-1(a) X X Function QX D FF CE X2
(a) How many logic blocks as shown in Figure 6-3 are required to create an 8-to-3 priority encoder?(b) Give the contents of the LUTs in the first logic block. Qх х, CE FF X2X Function Xout |
Show how to realize the following combinational function using two Figure 6-1(a) logic blocks. Show the connections on a copy of Figure 6-1(a) and give the functions X and Y for both blocks.F =
Realize the following next-state equation using a minimum number of Figure 6-1(a) logic blocks. Draw a diagram that shows the connections to the logic blocks and give the functions X and Y for each
Show how to realize the following next-state equations using a minimum number of the Kintex logic slice. Draw a diagram to show the connections between the logic elements and indicate how many CLBs
What is the minimum number of Figure 6-3 logic blocks required to realize the following function?X = X1'X2'X3'X4'X5 + X1X2X3X4X5 + X5'X6X7'X8'X' + X5'X6'X7X8X9'If your answer is 1, show the required
Illustrate how to realize the following equations using a minimum number of the Stratix IV logic module. Display the input/output by drawing a diagram and highlight the data path on the
Given Z(T, U, V, W, X, Y) = VW'X + U'V'WY + TV'WY',(a) Show how Z can be realized using a single Figure 6-3 logic block. Show the cell inputs on a copy of Figure 6-3; indicate the internal
Decompose the following function using Shannon’s decomposition around the variable X6. Do not simplify the function.F = X1’X2X3’X4X6 + X2’X3’X4X6’ + X2’X4’ + X3X4X5X6 + X3’X4X6’ +
Use Shannon’s expansion theorem around a and b for the function.Y = abcde + cde’f + a’b’c’def + bcdef ‘ + ab’cd’ef’ + a’bc’de’f + abcd’e’f.so that it
Use Shannon’s expansion theorem around e and f for the functionY = ab’cdef + a’bc’d’e + b’c’ef’ + abcde’fso that it can be implemented using a minimum number of
(a) Use Shannon's expansion theorem around a for the functionY = ab'cd'e + a'bc'd'e + b'c'e + abcdeso that it can be implemented using 4-variable functions.(b) Use the expanded function to show how Y
(a) If logic blocks of Figure 6-1(a) are used, how many LUTs are required to build a 4-bit adder with accumulator?(b) If an FPGA with built-in carry-chain logic as shown in Figure 6-11 is used, how
A 4 ⊗ 4 array multiplier (Figure 4-29) is to be implemented using an FPGA. (a) Partition the logic so that it fits in a minimum number of Figure 6-1(a) logic blocks. Draw loops around each set
(a) Use Shannon’s expansion theorem to expand the following function around A and then expand each sub-function around D:Z = AB’CD’E’F + A’BC’D’EF’ + B’C’E’F + A’BC’E’F’
(a) Indicate the connections of the switches in Figure 6-15 to realize the functionF = AB + A€™C(b) Indicate the connections of the switches in Figure 6-15 to realize a latch as shown in
The logic equations for a sequential network with five inputs, two flip-flops, and two outputs areQ1+ = Q1(Q2ABC) + Q1’(Q2’CDE)Q2+ = Q1’Z1 = Q1’Q2’AB + Q1’Q2’A’B’ + Q1Q2’AB’ +
Stratix IV and Stratix V are the popular Altera FPGAs on the market. Indicate the most significant differences between these chips’ logic modules
Show how 32 × 32-bit unsigned multiplication can be accomplished using four 16 × 16-bit multipliers and several adders. Draw a block diagram showing the required connections.
Fast shifting can be accomplished by using dedicated multipliers. Shifting left N places is equivalent to multiplying by 2N.(a) Given that A is a 16-bit unsigned number and 0 ≤ N ≤ 15, show how
Make a one-hot state assignment for Figure 4-53 and write the next-state and output equations by inspection. Then change the state assignment so that S0is assigned 0000000, S1is assigned
For the given state graph:(a) Derive the simplified next-state and output equations by inspection. Use the following one-hot state assignment for flip-flopsQ0Q+Q2Q3; S0, 1000; S1, 0100; S2, 0010; S3,
Consider the Verilog codemodule example(a,b);input[1:0] a;output[1:0] b;reg[1:0] b;always @(a)begincase(a)0: b 5 2’d3;1: b 5 2’d2;2: b 5 2’d1;3: b 5 2’d1;endcaseendendmodule(a) Show the
Draw the hardware structures that will be inferred by typical synthesizers from the code excerpts that follow. A, B, and E are 4-bit vectors, and C and D are 2-bit numbers; clock is a 1-bit signal.
(a) Draw a logic diagram (use gates, adders, MUXes, D flip-flops, etc.) that shows the result of synthesizing the following Verilog code. A, B, and C are 3-bitunsigned vectors.always @(negedge
Draw the hardware structures that will be inferred by typical synthesizers from the code excerpts that follow. If any ambiguities exist in the code, mention what you are assuming. Show optimized and
What hardware does the statementF = (A >= B);result in? Assume that A and B are 8-bit vectors.
Generate optimized hardware for the following statement, assuming A is a 4-bit vector: F = (A = 9);
(a) What is the biggest number that can be represented in the 8-bit 2’s complement floating-point format with 4 bits for exponent and 4 for fraction?(b) What is the smallest number that can be
Convert the following decimal numbers in the IEEE single precision format:(i) 25.25, (ii) 2000.22, (iii) 1, (iv) 0, (v) 1000, (vi) 8000, (vii) 106, (viii) -5.4,(ix)
Convert the following decimal numbers to IEEE double precision format:(i) 25.25, (ii) 2000.22, (iii) 1, (iv) 0, (v) 1000, (vi) 8000, (vii) 106, (viii) -5.4,(ix) 1.0
What do the following hex representations mean if they are in IEEE single precision format?(i) ABABABAB, (ii) 45454545, (iii) FFFFFFFF, (iv) 00000000, (v) 11111111,(vi) 01010101
What do the following hex representations mean if they are in IEEE double precision format?(i) ABABABAB 00000000, (ii) 45454545 00000001, (iii) FFFFFFFF 10001000,(iv) 00000000
(a) Represent -35.25 in IEEE single precision floating-point format. (b) What does the hex number ABCD0000 represent if it is in an IEEE single precision floating-point format?
(a) Represent 25.625 in IEEE single precision floating-point format.(b) Represent -15.6 in IEEE single precision floating-point format.
(a) Multiply the following two floating-point numbers to give a properly normalized result. Assume 4-bit 2’s complement format.F1 = 1.011, E1 = 0101, F2 = 1.001, E2 = 0011(b) Repeat (a)
A floating-point number system uses a 4-bit fraction and a 4-bit exponent with negative numbers expressed in 2’s complement. Design an efficient system that will multiply the number by -4 (minus
Redesign the floating-point multiplier in Figure 7. 7 using a common 5-bit full adder connected to a bus instead of two separate adders for the exponents and fractions.(a) Redraw the block diagram,
This problem concerns the design of a circuit to find the square of a floating-point number, F x 2E. F is a normalized 5-bit fraction, and E is a 5-bit integer; negative numbers are represented in
Write a behavioral Verilog code for a floating-point multiplier using the IEEE single precision floating-point format. Use an overloaded multiplication operator instead of using an add-shift
Add the following floating-point numbers (show each step). Assume that each fraction is 5 bits (including sign) and each exponent is 5 bits (including sign) with negative numbers in 2’s
Two floating-point numbers are added to form a floating-point sum:(F1 x 2E1) + (F2 x 2E2) = F x 2EAssume that F1 and F2 are normalized and the result should be
For the floating-point adder of Figure 7-14, modify the Verilog code so that(a) It handles IEEE standard single precision denormalized numbers both as input and output.(b) In state 2, it speeds up
a) Perform the floating point addition.b) Draw an SM chart for a floating-point adder that adds F1 x 2E1 and F2 x 2E2. Assume that the fractions are initially normalized (or zero) and the final
(a) Draw a block diagram for a floating-point subtracter. Assume that the inputs to the subtracter are properly normalized, and the answer should be properly normalized. The fractions are 8 bits
(a) State the steps necessary to carry out floating-point subtraction, including special cases. Assume that the numbers are initially in normalized form and the final result should be in normalized
This problem concerns the design of a divider for floating-point numbers:(F1 x 2E1)/(F2 x 2E2) = F x 2E Assume that F1 and F2 are properly
The block diagram for an elevator controller for a building with two floors is shown in the following diagram. The inputs FB1and FB2are floor buttons in the elevator. The inputs CALL1and CALL2are
Design a multiplier for 16-bit binary integers. Use a design similar to Figures 4-33 and 4-34.(a) Draw the block diagram. Add a counter to the control circuit to count the number of shifts.(b) Draw
Design a binary-to-BCD converter that converts a 10-bit binary number to a 3-digit BCD number. Assume that the binary number is ≤ 999. Initially the binary number is placed in register B. When an
Draw an SM chart for the binary multiplier of Problem 4.22.Data from Problem 4.22.Design a multiplier that will multiply two 16-bit signed binary integers to give a 32-bit product. Negative numbers
Draw an SM chart for the square root circuit of Problem 4.14.Data from Problem 4.14.This problem involves the design of a circuit that finds the square root of an 8-bit unsigned binary number N using
Draw an SM chart for the BCD-to-binary converter of Problem 4.13.Data from Problem 4.13.This problem involves the design of a BCD-to-binary converter. Initially a 3-digit BCD number is placed in the
(a) Draw the block diagram for a divider that divides an 8-bit dividend by a 5-bit divisor to give a 3-bit quotient. The dividend register should be loaded when St = 1.(b) Draw an SM chart for the
An association has 15 voting members. Executive meetings of this association can be held only if more than half (i.e., at least eight) of the members are present (i.e., eight is the minimum quorum
Find a minimum-row PLA table to implement the following sets of functions:(a) f1 (A, B, C, D) = ∑m(0, 2, 3, 6, 7, 8, 9, 11, 13), f2 (A, B, C, D) = ∑m(3, 7, 8, 9, 13), f3 (A, B, C,
(a) Find a minimum-row PLA table to implement the following equations:x (A, B, C, D) = ∑m(0, 1, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15)y (A, B, C, D) = ∑m(0, 1, 4, 5, 8, 10, 11, 12, 14, 15)z (A, B, C,
A D flip-flop has a setup time of 5 ns, a hold time of 3 ns, and a propagation delay from the rising edge of the clock to the change in flip-flop output in the range of 6 to 12 ns. An OR gate delay
What is the size of the smallest ROM that is needed to implement the following?(a) An 8-bit full adder (assume carry-in and carry-out)(b) A BCD-to-binary converter (2 BCD digits)(c) A 4-to-1 MUX(d) A
Given F = A'B' + BC' and G = AC + B', write a complete Verilog module that realizes the functions F and G using an 8-word x 2-bit ROM. Include the array type declaration and the constant declaration
Implement the following state table using a ROM and two D flip-flops. Use a straight binary state assignment. (a) Show the block diagram and the ROM truth table. Truth table column headings
The following state table is implemented using a ROM and two D flip-flops (falling edge triggered):(a) Draw the block diagram.(b) Write Verilog code that describes the system. Assume that the ROM has
Find a minimum-row PLA to implement the following three functions:f (A, B, C, D) = ∑m(3, 6, 7, 11, 15)g (A, B, C, D) = ∑m(1, 3, 4, 7, 9, 13)h (A, B, C, D) = ∑m(4, 6, 8, 10, 11, 12, 14, 15)Use
Write VHDL code that describes the output macrocell of a 22V10. The entity should include S1 and S0. The flip-flop has an asynchronous reset (AR) and a synchronous preset (SP).
An N-bit bidirectional shift register has N parallel data inputs, N outputs, a left serial input (LSI), a right serial input (RSI), a clock input, and the following control signals:Load: Load
Show how the left shift register of Figure 2-41 could be implemented using a CPLD. Draw a diagram. Give the equations for the flip-flop D inputs. always @ (posedge CLK) begin if (CLR) else if (Ld)
A Mealy sequential circuit with four output variables is realized using a 22V10. What is the maximum number of input variables it can have? What is the maximum number of states? Can any Mealy circuit
(a) What is the difference between a traditional gate array and an FPGA?(b) What are the different types of FPGAs based on architecture (organization)?(c) What are the different programming
(a) In which applications should a designer use a CPLD rather than an FPGA?(b) In which applications should a designer use an MPGA rather than an FPGA?(c) In which applications should a designer use
(a) Implement the function F1 = A'BC + B'C + ABC using an FPGA with programmable logic blocks consisting of 4-to-1 multiplexers. Assume inputs and their complements are available.(b) Implement the
Consider the following programmable I/O block:Highlight the connections to configure this I/O block as an INPUT pin. Specify the five configuration bits. CONFIGURATION BITS Vcc OUT 3-STATE LATCHED
Design the correction circuit for a BCD adder that computes Zdigit 0 and C for S0. This correction circuit adds 0110 to S0 if S0 > 9. This is the same as adding 0AA0 to S0, where A = 1 if S0 >
(a) If gate delays are 5ns, what is the delay of the fastest 4-bit ripple carry adder? (b) If gate delays are 5ns, what is the delay of the fastest 4-bit adder? What kind of adder will it be?
Develop a Verilog model for a 16-bit carry look-ahead adder utilizing the 4-bit adder from Figure 4-10 as a module.
Derive generates, propagates, group generates, group-propagates, and the final sum and carry out for the 16-bit carry look-ahead adder of Figure 4-9, while adding 0101 1010 1111 1000 and 0011 1100
(a) Write a Verilog module that describes one bit of a full adder with accumulator. The module should have two control inputs, Ad and L. If Ad = 1, the Y input (and carry input) are added to the
(a) Implement the traffic-light controller of Figure 4-14 using a module 13 counter with added logic. The counter should increment every clock, with two exceptions. Use a ROM to generate the

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